co561ad-s Connect One Ltd., co561ad-s Datasheet
co561ad-s
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co561ad-s Summary of contents
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... CO561AD-S Datasheet Pub. No. 11-3500-00, ©Copyright January 2003 Ver. 1.04 International: Connect One Ltd. 2 Hanagar Street Kfar Saba 44425, Israel Tel: +972-9-766-0456 Fax: +972-9-766-0461 E-mail: info@connectone.com http://www.connectone.com USA: Connect One Semiconductors, Inc. 15818 North 9th Ave. Phoenix, AZ 85023 Tel: 408-986-9602 Fax: 602-485-3715 E-mail: info@connectone ...
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... Connect One. iChip, iChip LAN, Socket iChip, Embedded iModem, Internet Controller, iLAN, iModem, Instant Internet, AT+i, and Connect One are trademarks of Connect One Ltd. Copyright 2000 - 2002 Connect One Ltd. All rights reserved. iChip CO561AD-S Datasheet ii ...
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... Revision History 11-3500-00 Version Date 1.00 November 2002 1.04 January 2003 iChip CO561AD-S Datasheet Description Changed data sheet format of publication 11-3100-07. Separated CO561AD-S and CO561AD-L data sheets. Updated pin descriptions. Internal Editing iii ...
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... Host Serial Connection ................................................................................ 3-2 3.2.6 Serial Connection to Analog Modem .......................................................... 3-3 3.2.7 Hardware and Software Flow Control ......................................................... 3-3 4 Hardware Interface................................................................................................. 4-1 4.1 Host Interface............................................................................................... 4-1 4.2 Serial Modem Interface................................................................................ 4-2 5 Pin Descriptions....................................................................................................... 5-1 5.1 iChip CO561AD-S Pin Assignments........................................................... 5-1 5.2 iChip Pin Functional Descriptions ............................................................... 5-2 5.2.1 Local BUS Signals 5.2.2 Miscellaneous Signals.................................................................................. 5-4 5.2.3 Host Interface Signals .................................................................................. 5-6 6 Electrical/Mechanical Specifications ..................................................................... 6-1 6.1 Environmental Specifications ...................................................................... 6-1 6.1.1 Absolute Maximum Ratings ...
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... Supervisory Circuit ...................................................................................... 7-2 8 Protocol Compliance ............................................................................................... 8-1 9 List of Terms and Acronyms.................................................................................. 9-1 iChip CO561AD-S Datasheet Contents v ...
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... Figure 1-1 iChip Functional Block Diagram................................................................... 1-2 Figure 4-1 iChip CO561AD-S with a Se rial Modem Interface ....................................... 4-2 Figure 5-1 PLCC68 Package for iChip CO 561AD-S Serial Version .............................. 5-1 Figure 6-1 Local BUS Read Cycle.................................................................................. 6-4 Figure 6-2 Local BUS Write Cycle................................................................................. 6-5 Figure 6-3 Clock Waveform............................................................................................ 6-5 Figure 6-4 Mechanical Dimensions................................................................................. 6-6 Figure 7-1 Serial Modem Environment........................................................................... 7-1 ...
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... Table 4-1 Host Data Format............................................................................................ 4-1 Table 6-1 Environmental Specifications for 5V and 3.3V Version ................................. 6-1 Table 6-2 DC Operating Characteristics 3.3V Version................................................... 6-2 Table 6-3 DC Operating Characteristics 5V Version...................................................... 6-2 Table 6-4 Switching Characteristic .................................................................................. 6-3 Table 8-1 Internet Protocol Compliance .......................................................................... 8-1 Table 9-1 Terms and Acronyms...................................................................................... 9-2 iChip CO561AD-S Datasheet Tables vii ...
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... Web site as well as a customizable application Web site. iChip also includes a WAP server to host a WAP site. When the host CPU issues standard AT commands, iChip CO561AD-S allows direct access to the modem by automatically operating in transparent mode, emulating a direct host-to-modem environment. When the host CPU issues AT+i commands, iChip enters into Internet mode and controls the modem connection to an ISP ...
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... Internal self-test procedures. ● ● Auto baud rate detection up to 115200 bps. ● Includes hardware and software flow control. PLCC68 package. ● iChip CO561AD-S Datasheet iChip 128 KB Rx,Tx,CTS,RTS DTR,DSR,CD Figure 1-1 iChip Functional Block Diagram General Protocols ● Supports following Internet Protocols: ...
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... Connect One’s iChip devices are available in two operating voltages. The order number is formed by a combination of the elements below: CO561AD-S Product Code Version SERIAL Clock 18.432 MHz Package PLCC 68 Pin Temperature Range Commercial (0 to70º 158° Voltage 3.3V iChip CO561AD-S Datasheet / – ...
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... CO561AD-S defaults to Transparent mode, allowing the host to control the modem device directly. Control is implemented by issuing standard AT commands to iChip. In this mode, iChip CO561AD-S transparently echoes the AT commands to the modem, as well as echoing the modem responses back to the host. In addition, hardware flow control ...
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... CO561AD-S instructs the modem to answer the call and assumes a YMODEM session to receive a file containing a firmware update. The incoming file contents are downloaded and authenticated. If the new firmware image checks out, the existing firmware is replaced in the on-chip flash memory and iChip CO561AD-S is reinitialized. 3.2.4 Remote Internet Firmware Update New firmware may be uploaded from a remote location using standard Internet protocols ...
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... Serial Connection to Analog Modem iChip CO561AD-S supports a full-duplex, TTL-level serial communications link with the modem device. Full EIA-232-D hardware flow control, including Tx, Rx, CTS, RTS, DTR, DSR and CD lines, is supported. It does not support the RI line. 3.2.7 Hardware and Software Flow Control Hardware flow control is supported between the host CPU and iChip and between iChip and the modem ...
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... Hardware Interface iChip CO561AD-S interfaces between a host CPU and a modem. 4.1 Host Interface The host interface is a serial DTE interface. Speeds of 2400, 4800, 9600, 19200, 38400, 57600 and 115200 bps are supported in the following data format: Parity None 1 Note: When hardware flow control is enabled the iChip transmitter will add an additional stop bit ...
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... Serial Modem Interface Rx,Tx, Host CTS,RTS,DTR,DSR, RI,CD Figure 4-1 iChip CO561AD-S with a Serial Modem Interface iChip CO561AD-S Datasheet Hardware Interface CPU Core Internal FLASH 512 KB Internal SRAM 128 KB Three 16-bit Timers Interrupt Rx,Tx, Controller CTS,RTS,DTR,DSR, CD Serial Modem 4-2 ...
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... AD2 5 AD1 6 AD0 7 A17 8 AD7 9 AD14 10 AD13 11 -RES 12 AD11 13 -UCS 14 -DSRH 15 AD10 16 AD9 17 Figure 5-1 PLCC68 Package for iChip CO561AD-S Serial Version iChip CO561AD-S Datasheet CO561AD Pin Descriptions A13 A19 A15 A12 A14 A5 A16 ...
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... O 14 -LCS O 21 iChip CO561AD-S Datasheet (*) Description Address BUS: These pins supply addresses to the system one-half of a CLKO period earlier than the multiplexed address and data BUS AD15–AD0. During a BUS hold or reset condition, the address BUS HIGH-impedance state. ...
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... (*)Note: Currently the local BUS is not in use in the CO561AD-S. iChip CO561AD-S Datasheet Description BUS HIGH Enable: This pin and the least-significant address bit (AD0 or A0) indicate to the system, which bytes of the data BUS (upper, lower, or both) participate in a BUS cycle. The ~BHE and A0 pins are encoded as shown in the table below ...
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... iChip CO561AD-S Datasheet Description UART Interrupt: This pin is for debugging purpose only. This pin should be pulled up to VCC. Modem Mode Select: • When this pin is held LOW during power up for at least 5 seconds, iChip will automatically enter firmware update mode. ...
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... CLKO O 44 GND P 67, 55 VCC P 1 iChip CO561AD-S Datasheet Description Clock Output: This pin outputs the internal clock of the system and has the some frequency as X2. Ground: Ground signal for iChip. Power Supply: This pin supplies power (+5V or +3.3V) to iChip. Pin Descriptions 5-5 ...
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... I 15 -DTRH O 63 iChip CO561AD-S Datasheet Description Transmit Data Host: This pin supplies asynchronous serial transmit data to the host. Receive Data Host: This pin supplies asynchronous serial receive data from the host. When this pin is not used, connect it to VCC. ...
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... Pin no. -CDH O 60 -RIH O 20 iChip CO561AD-S Datasheet Description Carrier Detect Host: This pin indicates to the host that the modem communication device detects a carrier signal. During firmware update, -CDH and -RIH are used to display the firmware update status. Ring Indicator Host: This pin indicates to the host that the modem communication device detects a Ring signal ...
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... O 18 -CDM I 66 iChip CO561AD-S Datasheet Description Transmit Data Modem: This pin provides asynchronous serial transmit data to the modem from the serial port. Receive Data Modem: This pin provides asynchronous serial receive data from the modem to the asynchronous modem serial port. ...
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... Voltage at any pin with respect to ground -0.5 to VCC + 0.5 Volts Operating temperature Storage temperature Soldering temperature (max. 10 sec.) Package dissipation Table 6-1 Environmental Specifications for 5V and 3.3V Version iChip CO561AD-S Datasheet Electrical/Mechanical Specifications Rating 0°C to 70°C (32 to 158°F) -60°C to 120°C (–76 to 248°F) 220°C (428°F) 1 ...
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... HIGH-level Input for X1 LOW-level Output 2 Input leakage current Power supply current (Operating Mode) 3 Input capacitance Notes 2.4mA 2mA MHz clock 3 Table 6-3 DC Operating Characteristics 5V Version iChip CO561AD-S Datasheet Electrical/Mechanical Specifications Min Typical Max 3.0 3.3 3.6 2.0 VCC+0.5 VCC-0.8 VCC+0.5 -0.5 0.8 VCC-0.5 VCC 0.45 +/- ...
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... X1 rise time (2) X1 LOW time X1 HIGH time X1 to CLKO skew (1) Fall time on 5V version is from 3. and on 3V version is from 2V to 1V. (2) Rise time on 5V version is from 1V to 3.5V and on 3V version is from 1V to 2V. iChip CO561AD-S Datasheet Electrical/Mechanical Specifications Symbol Min. Typical Fclk 18 ...
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... Local BUS Read Cycle Tclk CLKO Tavrl Address A19-A0 AD15-AD0 (Read) UCS LCS ALE ~RD ~BHE iChip CO561AD-S Datasheet Electrical/Mechanical Specifications Tdvcl Trlrh Tclrl ~BHE Figure 6-1 Local BUS Read Cycle Data Tcldx 6-4 ...
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... Tclk CLKO Tavwl Address A19-A0 AD15-AD0 (Write) Tcldv UCS LCS ALE -WR -BHE 6.2.4 Clock Waveform X2 X1 CLKO Tcklh iChip CO561AD-S Datasheet Electrical/Mechanical Specifications Data Twlwh Tcvctv ~BHE Figure 6-2 Local BUS Write Cycle Tchck Tclck Tckhl Tchck Tcico Figure 6-3 Clock Waveform Tcldox Tcvctx 6-5 ...
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... Mechanical Dimensions 1.27mm / 0.050” 24.5mm / 0.965” 4 0.193” 2. 0.106” Figure 6-4 Mechanical Dimensions iChip CO561AD-S Datasheet Electrical/Mechanical Specifications 0 0.020” CO561AD-S iChip 25.2mm / 0.995” 1. 0.070” 6-6 ...
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... The recommended range of values for C 1 and C 2 are as follows ............................................................... 15 pF ± 20 ............................................................... 22 pF ± 20% The specific values for C1 and C2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. iChip CO561AD-S Datasheet Data iChip Serial Serial ...
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... Supervisory Circuit Vcc Vcc R1 C11 4.7K 0.1UF GND PFI GND MAX708R GND C15 + 1UF/16V GND Figure 7-4 Supervisory Reset Circuit iChip CO561AD-S Datasheet τ should be greater than 10 mSec. 10K -RES 10U Figure 7-3 RC Reset Circuit RESET 7 -RES RESET 5 PFO iChip Designs 7-2 ...
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... Protocol Compliance iChip CO561AD-S complies with the following Internet standards: User Datagram Protocol (UDP) RFC 768 Internet Protocol (IP) RFC 791 RFC 792 ICMP – Internet Control Message Protocol RFC 793 Transmission Control Protocol (TCP) RFC 821 Simple Mail Transfer Protocol (SMTP) ...
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... Request For Comments. Collections of standards that define the way remote RFC computers communicate over the Internet. SMTP Simple Mail Transfer Protocol. Provides for transferring mail reliably and efficiently over the Internet. iChip CO561AD-S Datasheet Protocol Compliance 9-1 ...
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... TCP Transmission Control Protocol. Provides reliable stream-oriented connections over the Internet. Works in conjunction with its underlying IP protocol. Network Terminal Protocol. Provides remote terminal connectivity, which Telnet allows to execute tasks on a remote application server. iChip CO561AD-S Datasheet Table 9-1 Terms and Acronyms Index 9-2 ...