co661al-d Connect One Ltd., co661al-d Datasheet
co661al-d
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co661al-d Summary of contents
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... Plus iChip Plus CO661AL-D Datasheet Pub. No. 11-3400-01, ©Copyright February 2003 TM Ver. 1.03 International: Connect One Ltd. 2 Hanagar Street Kfar Saba 44425, Israel Tel: +972-9-766-0456 Fax: +972-9-766-0461 E-mail: info@connectone.com http://www.connectone.com USA: Connect One Semiconductors, Inc. 15818 North 9th Ave. ...
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... Connect One. iChip, iChip LAN, iChip Plus, Socket iChip, Embedded iModem, Internet Controller, iConnector, iLAN, iModem, Instant Internet, AT+i, and Connect One are trademarks of Connect One Ltd. Copyright 2000 - 2003 Connect One Ltd. All rights reserved. iChip Plus CO661AL-D Datasheet ii ...
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... Revision History 11-3400-01 Version Date 1.00 December 2002 1.02 February 2003 1.03 February 2003 iChip Plus CO661AL-D Datasheet Description Original Release for iChip Plus CO661AL-D Internal Editing Change POBE pin description iii ...
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... Introduction ............................................................................................................. 1-1 2 Ordering Information ............................................................................................. 2-1 2.1 iChip Plus CO661AL-D Order Number: ..................................................... 2-1 3 Functional Description............................................................................................ 3-1 3.1 Overview...................................................................................................... 3-1 3.2 Technical Specifications .............................................................................. 3-1 3.2.1 General......................................................................................................... 3-1 3.2.2 Operation...................................................................................................... 3-1 3.2.3 Remote Internet Firmware Update............................................................... 3-2 3.2.4 Local BUS Connection to an Ethernet LAN Controller .............................. 3-2 3.2.5 Host Connection........................................................................................... 3-2 3.2.6 Serial Connection to Analog Modem .......................................................... 3-3 3.2.7 Hardware and Software Flow Control ......................................................... 3-3 4 Hardware Interface................................................................................................. 4-1 4.1 Serial Host Interface .................................................................................... 4-1 4 ...
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... Parallel BUS Write Cycle ............................................................................ 6-5 6.3 Mechanical Dimensions............................................................................... 6-6 7 iChip Plus Designs................................................................................................... 7-1 7.1 Serial Host and Ethernet controller Environment ........................................ 7-1 7.2 Parallel Host and Ethernet controller Environment ..................................... 7-1 7.3 Selecting a Crystal ....................................................................................... 7-2 7.4 Selecting the Reset Circuit........................................................................... 7-3 7.4.1 RC Network ................................................................................................. 7-3 7.4.2 Supervisory Circuit ...................................................................................... 7-3 7.5 Sleep Mode .................................................................................................. 7-4 8 Protocol Compliance ............................................................................................... 8-1 9 List of Terms and Acronyms.................................................................................. 9-1 iChip Plus CO661AL-D Datasheet Contents v ...
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... Figure 1-1 iChip Plus Functional Block Diagram........................................................... 1-2 Figure 4-1 Interface to an 80x86 Type BUS .................................................................... 4-2 Figure 4-2 Interface to an MC68xxx Type BUS............................................................. 4-3 Figure 4-3: iChip Plus CO661AL-D with L AN and serial modem interface .................. 4-1 Figure 5-1 PLCC68 Package for iChip Plus CO661AL-D.............................................. 5-1 Figure 6-1 Local BUS Read Cycle.................................................................................. 6-3 Figure 6-2 Local BUS Write Cycle................................................................................. 6-3 Figure 6-3 Clock Waveform ...
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... Table 4-1 Host Data Format............................................................................................ 4-1 Table 4-2 Modem Data Format . ....................................................................................... 4-4 Table 6-1 Environmental Specificati o ns – Maximum Ratings........................................ 6-1 Table 6-2 DC Operating Characteristics .......................................................................... 6-1 Table 6-3 Switching Characteristics................................................................................ 6-2 Table 8-1 Internet Protocol Compliance .......................................................................... 8-1 Table 9-1 Terms and Acronyms...................................................................................... 9-2 iChip Plus CO661AL-D Datasheet Tables vii ...
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... Kbytes burst with up to 400 Kbytes sustained bandwidth in Parallel mode. iChip Plus CO661AL-D Datasheet CO661AL-D features power save modes and will have an extended temperature range version. Through its host Application Programming Interface (API), iChip Plus accepts commands formatted in Connect One's AT+i™ ...
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... Sleep Mode (with external glue logic). ● Auto baud rate detection up to 115,200 bps. ● Support for 230,400 bps (without auto baud rate). ● Supports hardware and software flow control. ● PLCC68 package. iChip Plus CO661AL-D Datasheet D0-D15 SRAM 128 KB A0-A19 -RD -WR CPU LANINT Core ...
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... Ordering Information 2.1 iChip Plus CO661AL-D Order Number: CO661AL-D /20 P Product Code Version Dual Typical Clock Rate 18.432 MHz Package PLCC 68 Pin Temperature Range Commercial (0 to70º 158° F) Voltage 3.3V iChip Plus CO661AL-D Datasheet Ordering Information C – 3 2-1 ...
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... FTP and Telnet, serve as a serial-to-Internet router manipulate sockets through a linked modem or Ethernet communications platform. For 10BaseT Ethernet applications, iChip Plus CO661AL-D includes the firmware and pin-out necessary to drive an external Crystal LAN CS8900A. For 10/100BaseT Ethernet applications, iChip Plus includes the firmware and pin-out necessary to drive an external SMSC LAN91C111 or ASIX AX88796L Ethernet LAN controller ...
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... Plus’ Web server. 3.2.4 Local BUS Connection to an Ethernet LAN Controller iChip Plus interfaces an Ethernet LAN controller connected to its 16-bit local BUS. 3.2.5 Host Connection iChip Plus can interface a host processor through one of two methods: Serial or Parallel. iChip Plus CO661AL-D Datasheet Functional Description 3-2 ...
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... Full EIA-232-D hardware flow control, including Tx, Rx, CTS, RTS, DTR, DSR, CD and RI lines, is supported. CO661AL-D supports standard baud rate configurations from 2,400 bps up to 230,400 bps on the host asynchronous serial communications channel. The default baud rate may be changed permanently by using the AT+iBDRF command. Auto baud rate setting is supported for all baud rates except 230,400 ...
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... Hardware Interface iChip Plus CO661AL-D may interface a host CPU in one of two methods: Serial or Parallel. The actual interface depends on the state of the –SER/PAR pin. 4.1 Serial Host Interface The host interface is a serial DTE interface. Speeds of 2400, 4800, 9600, 19200, 38400, 57600, 115200 and 230400 bps are supported in the following data format: ...
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... Plus. When the host reads the data, this signal goes LOW. This pin may be connected to an interrupt or I/O pin on the 80x86. Note 1: HOBE and HIBF complement PIBF and POBE respectively. iChip Plus CO661AL-D Datasheet Hardware Interface EPM7032AEC44 iChip Plus ...
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... Plus. When the host reads the data, this signal goes low. This pin may be connected to an interrupt or I/O pin on the MC68xxx. Note 1: HOBE and HIBF complement PIBF and POBE respectively. iChip Plus CO661AL-D Datasheet Hardware Interface EPM7032AEC44 iChip Plus ...
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... When iChip Plus operates in Parallel mode, the modem interface baud rate must be preprogrammed. All serial modem input signals (RXDM, -DSRM, -CTSM, -CDM) are 5V tolerant. iChip Plus does not provide a Ring Indicator input signal. iChip Plus CO661AL-D Datasheet Data Length No. of (No. of Bits) ...
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... Dual Interface Rx,Tx, HOST CTS,RTS,DTR,DSR Figure 4-3: iChip Plus CO661AL-D with LAN and serial modem interface iChip Plus CO661AL-D Datasheet CPU Core Internal FLASH 512 KB Internal SRAM 128 KB Three 16-bit Timers Local Bus Interrupt Controller Rx,Tx, CTS,RTS,DTR,DSR, Hardware Interface LAN RJ45 Controller Serial Modem ...
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... A17 D14 10 D13 11 -RES 12 D11 -DSRH/-PRES 15 D10 Figure 5-1 PLCC68 Package for iChip Plus CO661AL-D iChip Plus CO661AL-D Datasheet iChip Plus CO661AL Pin Descriptions A13 A19/Z7 A15 A12 A14 A5 ...
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... O 31 iChip Plus CO661AL-D Datasheet Description Address BUS: These pins supply addresses to the system. These pins should be Connected to the address BUS of the LAN controller. Address BUS MSB. This pin should be connected to the LAN controller’s address BUS MSB ...
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... Type Pin No iChip Plus CO661AL-D Datasheet Description READ: This pin indicates that iChip Plus is performing a read cycle. This pin should be connected to -RD on the LAN controller. WRITE: This pin indicates that iChip Plus is performing a write cycle. This pin should be connected to -WR on the LAN controller ...
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... CLKO/HBT/Z6 O -SER/PAR I iChip Plus CO661AL-D Datasheet Description 12 RESET: When -RES is LOW, iChip Plus immediately terminates its present activity and clears its internal logic. -RES must be held LOW for at least 1 mSec after power achieves 90% VCC. This input is provided with a Schmidt trigger to facilitate power-on reset generation via an RC network ...
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... Z5 I/O 62 GND P 67 VCC P iChip Plus CO661AL-D Datasheet Description LAN Interrupt. When HIGH, this signal indicates that the LAN controller has information for iChip Plus. GPIO for future use. This pin should be Not Connected. In Serial mode available as a GPIO for future use and should be left Not Connected ...
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... I 59 -RTSH/-PERR O 58 iChip Plus CO661AL-D Datasheet Description In Serial mode, Transmit Data Host: This pin supplies asynchronous serial transmit data to the host. In Parallel mode, this pin is used for firmware update. In Serial mode, receive Data Host: This pin supplies asynchronous serial receive data from the host ...
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... O 60 -RIH/-SER O 20 iChip Plus CO661AL-D Datasheet Description In Serial mode, Data Set Ready Host: when -DSRH is LOW, it indicates that the host is attached and ready to communicate with iChip Plus. Connect -DSRH to GND when not in use. In Parallel mode, Parallel Reset: when LOW, generates a reset to the parallel interface. After reset this pin’ ...
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... O 18 -CDM I 66 iChip Plus CO661AL-D Datasheet Description Transmit Data Modem: this pin provides asynchronous serial transmit data to the modem from the serial port. During reset, this pin must remain high. Receive Data Modem: this pin provides asynchronous serial receive data from the modem to the asynchronous modem serial port ...
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... Notes 2mA 2mA 18.432 MHz clock 3 Table 6-2 DC Operating Characteristics iChip Plus CO661AL-D Datasheet Electrical/Mechanical Specifications Rating -0.5 to +3.8 Volts -0.5 to +5.5 Volts 0°C to 70°C (32 to 158°F) -60°C to 120°C (–76 to 248°F) 220°C (428°F) 1.5 Watts Min Typical Max 3 ...
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... RXDM high after rising reset Read rising to input parallel buffer full Write rising to output parallel buffer empty Table 6-3 Switching Characteristics 1 Fall time is from 2.3V to 1V. 2 Rise time is from 1V to 2.3V. iChip Plus CO661AL-D Datasheet Electrical/Mechanical Specifications Symbol Min. Typical Fclk 18.43 18.432 Tclk 1/Fck Txfac 4 ...
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... Tclk X2 Txfac A18-A0 -BHE D15-D0 (Write) Txrdv -FCS or -RCS * -WR Txrwa * -FCS and –RCS are internal Flash and RAM Chip-select. iChip Plus CO661AL-D Datasheet Electrical/Mechanical Specifications Txfac Address Data Tdsarh Tdsbrh Txfri Figure 6-1 Local BUS Read Cycle Txfac Address Data Tdovaw Txfwi ...
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... Clock Waveform X1 X2 CLKOUT Tckhl 6.2.5 Reset Timing -RES Don't care TXDM iChip Plus CO661AL-D Datasheet Electrical/Mechanical Specifications Tchck Tclck Tcico Tcklh Figure 6-3 Clock Waveform Trst Trmar Trmbr Figure 6-4 Reset Timing Don't care 6-4 ...
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... PCS -RD PIBF -WR*-CS Host Figure 6-5 Parallel BUS Read Cycle 6.2.7 Parallel BUS Write Cycle X2 Txfac D7-D0 (Write) PCS Txrdv -WR POBE -RD*-CS Host Figure 6-6 Parallel BUS Write Cycle iChip Plus CO661AL-D Datasheet Electrical/Mechanical Specifications Txfac Data Tdsbrh Txrra Trrbf Txfri Data Tdovaw Twrbe Txfri Tdsarh 6-5 ...
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... Mechanical Dimensions 1.27mm / 0.050” 24.5mm / 0.965” 4 0.193” 2. 0.106” Figure 6-7 Mechanical Dimensions iChip Plus CO661AL-D Datasheet Electrical/Mechanical Specifications 0 0.020” CO661AL-D TM iChip Plus 25.2mm / 0.995” 1. 0.070” 6-6 ...
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... Serial CPU (Host) Plus Figure 7-1 Serial Host and Ethernet Controller Environment 7.2 Parallel Host and Ethernet controller Environment Embedded CPU (Host) PAL Parallel Figure 7-2 Parallel Host and Ethernet Controller Environment iChip Plus CO661AL-D Datasheet D0-D15 A0-A19 -RD -WR LANINT Modem Serial D0-D15 A0-A19 ...
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... The recommended range of values for C 1 and C 2 are as follows ............................................................... 15 pF ± 20 ............................................................... 22 pF ± 20% The specific values for C1 and C2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design. iChip Plus CO661AL-D Datasheet X1 Crystal X2 Figure 7-3 Selecting a Crystal ...
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... Supervisory Circuit Vcc Vcc R1 C11 4.7K 0.1UF GND PFI GND MAX708R GND C15 + 1UF/16V GND Figure 7-5 Supervisory Reset Circuit iChip Plus CO661AL-D Datasheet τ should be greater than 10 mSec. 10K -RES 10U Figure 7-4 RC Reset Circuit RESET -RES 7 RESET 5 PFO iChip Designs 7-3 ...
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... Sleep Mode CO661AL-D iChip Plus supports a sleep mode when iChip Plus is not in use. Sleep mode is based on an external circuit that gates the oscillator input to iChip Plus. The PWSG (pin 41 output pin used to trigger Sleep mode. While in this mode, iChip Plus current consumption is reduced to ~1 mA. The ...
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... Protocol Compliance iChip Plus CO661AL-D complies with the following Internet standards: User Datagram Protocol (UDP) RFC 768 Internet Protocol (IP) RFC 791 RFC 792 Internet Control Message Protocol RFC 793 Transmission Control Protocol (TCP) RFC 821 Simple Mail Transfer Protocol (SMTP) RFC 826 Ethernet Address Resolution Protocol ...
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... PC) users through a dial-up connection. LAN Local Area Network. HIGH-speed, LOW-error data network covering a relatively small geographic area ( few thousand meters). Link Control Protocol. Negotiates data link characteristics and tests the LCP integrity of the link. iChip Plus CO661AL-D Datasheet List of Terms and Acronyms 9-1 ...
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... Internet. Works in conjunction with its underlying IP protocol. An option designating whether retrieved Email messages are to be left intact "Leave on on the server for subsequent downloads or are to be deleted from the server Server" after a successful download. iChip Plus CO661AL-D Datasheet List of Terms and Acronyms Table 9-1 Terms and Acronyms 9-2 ...