w86l488y-ay Winbond Electronics Corp America, w86l488y-ay Datasheet - Page 23

• Manufacturer Part Number: w86l488y-ay
• Description: Winbond Host Interface Sd/sdio/mmc Memory Card Bridge
• Manufacturer: Winbond Electronics Corp America

Data Access Request (XDRQN):
Data Aaccess Request is used to notify the Host to access transmit or receive buffers. The Data
Access Request can be activated both in Type 1 and Type 2.
During host transmits data to the card, the XDRQN will be asserted if the data write command has
been transfer to the card and the transmit data buffer have not enough data to transmit to the card.
The XDRQN will not be asserted if the transmit data buffer have enough data to transmit to the card.
The last byte of the data should be placed at bit [15:8] if the data length is odd byte and CPU data
size is 16-bit.
During host receives data from the card, the XDRQN will be asserted if the data read command has
been transferred to the card and the data have been received in the receive data buffer. The XDRQN
will not be asserted if the data read command has been executed completely and the receive data
buffer is read out. The last byte of the data is located at bit [7:0] if the data length is odd byte and CPU
data size is 16-bit.
There are two types of data access request waveform, Single and Burst Access Mode.
Single Access Mode is configured if DABST = low, XDRQN will be de-asserted after each access
receive or transmit data buffer, the XDRQN will be activated again after four clock period later. Figure
7-5 shows the waveform of Host access receive data buffer in single access mode (DABST = low).
Burst Access Mode is configured if DABST = high, XDRQN will hold at active state until the data has
been transferred completely. The Host can access receive or transmit data buffer with higher speed
continuously and regardless of the system clock. Figure 7-6 is the waveform of Host access transmit
data buffer in burst mode (DABST = high).
Fig. 7-5 Host Read Receive Data Buffer in Single Access Mode (DABST = low).
A[3:1]
D[15:0]
XCSN
XRDN
XDRQN
System
Clock
010
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010
W86L488