hys64d16020gd Infineon Technologies Corporation, hys64d16020gd Datasheet
hys64d16020gd
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Edition 2004-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, Edition 2004-01 81669 München, Germany Published by Infineon Technologies AG, Infineon Technologies AG 2004. © St.-Martin-Strasse 53, All Rights Reserved. 81669 München, Germany Attention please! Infineon Technologies AG 2004. © All ...
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... Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com Data Sheet Data Sheet HYS64D16020GD(L)-[7/8]-A Unbuffered DDR SDRAM SO Modules 4 4 2004-01 Rev. 1.02, 2004-01 ...
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... Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data Sheet HYS64D16020GD(L)-[7/8]-A Unbuffered DDR SDRAM SO Modules 5 11042003-YIV7-VK6M Rev. 1.02, 2004-01 ...
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... PC board. The DIMMs feature serial presence detect based serial E PROM device using the 2-pin I data and the second 128 bytes are available to the customer. Data Sheet HYS64D16020GD(L)-[7/8]-A Unbuffered DDR SDRAM SO Modules –7 DDR266A PC2100-2033 f 143 CK2 ...
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... The Compliance Code which is printed on the module labels describes the speed sort class (“for example PC2100”), the latencies (for example 20330 means CAS latency = 2, trcd latency = 3 and trp latency = 3) and the Raw Card used for this module Data Sheet HYS64D16020GD(L)-[7/8]-A Unbuffered DDR SDRAM SO Modules Description SDRAM Technology ...
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... Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not Connected Note: S1 and CKE1 are used on two rank modules only Data Sheet HYS64D16020GD(L)-[7/8]-A Unbuffered DDR SDRAM SO Modules Function Address Inputs Bank Selects Data Input/Output Check Bits (×72 organization only) ...
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... A6 DQ50 126 DQ28 DQ51 127 DQ29 V V 128 SS DDQ V 129 DM3/DQS12 DDID DQ56 130 A3 DQ57 131 DQ30 9 HYS64D16020GD(L)-[7/8]-A Pin Configuration PIN# Symbol 140 NC / DM8/DQS17 141 A10 142 NC / CB6 143 V DDQD 144 NC / CB7 Key 145 V SS 146 DQ36 147 DQ37 148 ...
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... NC 137 CK0 SDA 138 CK0 SCL 139 V SS SDRAMs # of SDRAM # of SDRAMs density row/rank/ columns bits 8M × 128Mbit 12/2/9 10 HYS64D16020GD(L)-[7/8]-A Pin Configuration PIN# Symbol 177 DM7/DQS16 178 DQ62 179 DQ63 180 V DDQ 181 SA0 182 SA1 183 SA2 184 V DDSPD Refresh Period Interval ...
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... I/O 11 DQ59 I/O 12 I/O 12 DQ60 I/O 13 I/O 13 DQ61 I/O 14 I/O 14 DQ62 I/O 15 I/O 15 DQ63 Ω ± and HYS64D16020GD(L)-[7/8]-A Pin Configuration Serial Presence Detect (SPD) SCL SA0 A0 SDA SA1 A1 SA2 A2 WP CK0 4 loads CK0 CK1 4 loads CK1 CK2 0 loads CK2 Note: DQ wiring may differ from that described in this drawing ...
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... Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Data Sheet HYS64D16020GD(L)-[7/8]-A Unbuffered DDR SDRAM SO Modules Electrical Characteristics Symbol Values min ...
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... also expected to track noise variations in REF (DC) REF system supply for signal termination resistors, is expected to be set equal REF V stabilizes. REF 13 HYS64D16020GD(L)-[7/8]-A Electrical Characteristics 1) Unit Note/Test Condition — V — 7) — ...
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... DQ, DQS and DM; IN REF ≤ . IH,MIN IL,MAX for DQ, DQS and DM. ILMAX IN REF IH,MIN RC RAS,MAX OUT 14 HYS64D16020GD(L)-[7/8]-A Electrical Characteristics Symbol I DD0 I DD1 I DD2P I DD2F for DQ, DQS and DM. I DD2Q I DD3P I DD3N I DD4R I DD4W I DD5 I DD6 I DD7 Rev. 1.02, 2004-01 11042003-YIV7-VK6M ...
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... I and can be measured differently according to DQ loading ° values of the component data sheet as follows: DDx I data sheet values as × DDx 15 HYS64D16020GD(L)-[7/8]-A Electrical Characteristics 1)2) Note 3)4) I [component] DDx Rev. 1.02, 2004-01 11042003-YIV7-VK6M ...
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... DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Data Sheet HYS64D16020GD(L)-[7/8]-A Unbuffered DDR SDRAM SO Modules Symbol –8 –7 DDR200 DDR266A Min Max ...
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... XSNR t 200 — 200 XSRD t — 7.8 — REFI V = +2.5 V ± 0 CK/CK slew rate are ≥ 1.0 V/ns. REF V stabilizes. REF 17 HYS64D16020GD(L)-[7/8]-A Electrical Characteristics –7 Unit Note/ 1) Test Condition Max. 2)3)4)5) — — ns fast slew rate 3)4)5)6)10) — ns slow slew rate 3)4)5)6)10) — ns fast slew rate 3)4)5)6)10) — ...
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... For each of the terms, if not already an integer, round to the next highest integer. cycle time. 14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Data Sheet Unbuffered DDR SDRAM SO Modules . 18 HYS64D16020GD(L)-[7/8]-A Electrical Characteristics t . DQSS t is equal to the actual system clock CK Rev ...
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... Min. Clock Cycle Time at CAS Latency = 2 24 Access Time from Clock for Minimum Clock Cycle Time for CL = 1.5 26 Access Time from Clock 1.5 27 Minimum Row Precharge Time Data Sheet HYS64D16020GD(L)-[7/8]-A Unbuffered DDR SDRAM SO Modules 128MB x64 2ranks –7 HEX. 128 80 256 08 DDR-SDRAM 07 12 ...
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... Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number 99 to 127 – 128 to 255 open for Customer use Data Sheet HYS64D16020GD(L)-[7/8]-A Unbuffered DDR SDRAM SO Modules RCD t 45 ns/50 ns RAS 0.9 ns/1.1 ns 0.5 ns/0.6 ns 0.5 ns/0.6 ns – t ...
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... MIN. Detail of contacts 0.6 ±0.1 Burnished, no burr allowed Figure 3 Package Outlines Raw Card A : DDR-SDRAM SO-DIMM Modules Raw Card A Data Sheet Unbuffered DDR SDRAM SO Modules 67.6 63.6 ±0.1 (2.45) 100 ±0.1 47.4 ±0.1 (2.15) 200 0.45 ±0.03 21 HYS64D16020GD(L)-[7/8]-A Package Outlines 3.8 MAX. 1 ±0.1 0.15 Rev. 1.01, 2003-11 11042003-YIV7-VK6M ...
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Published by Infineon Technologies AG ...