gs8662dt11bgd-500i GSI Technology, gs8662dt11bgd-500i Datasheet - Page 20

• Manufacturer Part Number: gs8662dt11bgd-500i
• Description: 72mb Sigmaquad-ii+tm Burst Of 4 Sram
• Manufacturer: GSI Technology

AC Electrical Characteristics (x18/x36)
Rev: 1.00 5/2011
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Clock
K, K Clock Cycle Time
tK Variable
K, K Clock High Pulse Width
K, K Clock Low Pulse Width
K to K High
K to K High
DLL Lock Time
K Static to DLL reset
Output Times
K, K Clock High to Data Output Valid
K, K Clock High to Data Output Hold
K, K Clock High to Echo Clock Valid
K, K Clock High to Echo Clock Hold
CQ, CQ High Output Valid
CQ, CQ High Output Hold
CQ, CQ High to QLVD
CQ Phase Distortion
K Clock High to Data Output High-Z
K Clock High to Data Output Low-Z
Setup Times
Address Input Setup Time
Control Input Setup Time
(R/W, LD)
Control Input Setup Time
(BWX)
Data Input Setup Time
Hold Times
Address Input Hold Time
Control Input Hold Time
(R/W, LD)
Control Input Hold Time
(BWX)
Data Input Hold Time
Notes:
1.
2.
3.
4.
5.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
Control signals are R/W, LD.
Control signals are BW0, BW1 and (BW2, BW3 for x36).
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
V
DD
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V
Parameter
Symbol
t
t
t
t
t
t
CQHCQH
CQHCQH
t
t
t
t
KHCQV
KHCQX
CQHQV
CQHQX
t
t
t
t
t
t
t
t
KHQX1
t
t
t
t
KReset
t
KHQV
KHQX
t
t
t
t
KHKH
KHKL
KLKH
KHKH
KHKH
KLock
QVLD
KHQZ
AVKH
DVKH
KHAX
KHDX
KVar
IVKH
IVKH
KHIX
KHIX
–0.45
–0.29
–0.15
–0.15
0.655
–0.45
2048
1.81
0.77
0.77
0.23
0.23
0.18
0.18
0.23
0.23
0.18
0.18
Min
0.4
0.4
—
30
—
—
—
—
-550
Max
0.15
0.45
0.29
0.15
0.15
0.45
8.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/34
–0.45
–0.33
–0.15
–0.15
–0.45
2048
Min
0.85
0.85
0.75
0.25
0.25
0.20
0.20
0.25
0.25
0.20
0.20
2.0
0.4
0.4
30
—
—
—
—
—
-500
Max
0.15
0.45
0.33
0.15
0.15
0.45
8.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GS8662DT20/38BD-550/500/450/400/350
–0.45
–0.37
–0.15
–0.15
–0.45
0.275
0.275
0.275
0.275
2048
Min
0.94
0.94
0.85
0.22
0.22
0.22
0.22
2.2
0.4
0.4
30
—
—
—
—
—
-450
GS8662DT06/11BD-500/450/400/350
Max
0.15
0.45
0.37
0.15
0.15
0.45
8.4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–0.45
–0.45
–0.45
2048
Min
1.06
1.06
–0.2
0.28
0.28
0.28
0.28
-0.2
2.5
0.4
0.4
1.0
0.4
0.4
0.4
0.4
30
—
—
—
—
—
-400
DD
Max
0.45
0.45
0.45
8.4
0.2
0.2
0.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
and input clock are stable.
–0.45
–0.45
–0.23
–0.23
–0.45
2048
Min
2.86
1.13
1.13
0.28
0.28
0.28
0.28
0.4
0.4
1.0
0.4
0.4
0.4
0.4
30
—
—
—
—
—
© 2011, GSI Technology
-350
Max
0.45
0.45
0.23
0.23
0.45
8.4
0.2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
cycle
cycle
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
5
1
2
3
1
2
3