w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 14

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
WINBOND ELECTRONICS CORP. AMERICA
Pin Name
PCICLK
A20M# /
PCIRST#
AD[31:0]
C/BE[3:0]#
Pin #
23
22
29-31,33-37,41-
44, 46,47, 49,
50, 62-67,
69,71,73 -
79,81
39, 51, 61,
72
RSTDRV
HREST#
does not
Note:
affect
Buffer
Type
I
O
I/O
I/O
Table 2-2. PCI Bus Signals
Description
CLOCK. Provides timing for all transactions on the PCI bus. Also
it is internally divided down to generate BCLK for the ISA bus.
ADDRESS BIT 20 MASK or PCI RESET.
In X86 mode, it functions as ADDRESS BIT 20 MASK in x86
mode. A20M# is asserted when I/O port 92h or port 60h/64h A20
sequence is active. See description of Function 0 Configuration
Space Register index 4Eh for detail.
It functions as PCI RESET in PowerPC mode. It is driven active for
one millisecond following one of these events:
PCIRST# is inverted internally to generate ISARST on the ISA bus
in PowerPC mode.
PCI ADDRESS/DATA. AD[31:0] is a multiplexed address/data
bus. A valid 32-bit address is available during the address phase of a
PCI transaction. All subsequent cycles (i.e. data phase) will contain
the data. Little-endian byte ordering is used. AD[7:0] contains the
least significant byte. AD[31:24] contains the most significant byte.
As an initiator, it drives a valid 32-bit address on AD[31:0] in the
address phase. It drives write data or latches read data on AD[31:0]
during the data phase.
As a target, it decodes the address on AD[31:0] during the address
phase and may latch the write data or drives the read data on
AD[31:0] in the data phase.
Bus Command and Byte Enables. These bits are multiplexed on the
same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase,
C/BE[3:0]# are used for byte enables.
- PWRGD goes from logic low to high
- HOT RESET bit is set (Port 92h, bit 0)
- RSTDRV bit is set (Function 0 Configuration Space index 4Ch
bit 3)
Pin Descriptions
12