w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 20

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
WINBOND ELECTRONICS CORP. AMERICA
Pin Name
IDEIOWB#
IDEIORB#
IDEDRQA
IDEDAKA#
IDEDRQB
IDEDAKB#
Pin #
84
82
97
94
96
93
Table 2-4 (continued). IDE Interface Bus Signals
Input/
Output
Output
Output
Input
Output
Input
Output
Description
Multi-function pin.
In PIO and Multiword DMA modes: Drive I/O Write B. This signal
is used jointly with IDECS0# and IDECS1#. The rising edge of
IDEIOWB# latches data into the secondary port IDE device.
In UltraDMA mode: STOPA. This signal is used to terminate an
UltraDMA transaction by 554F.
Multi-function pin.
In PIO and Multiword DMA modes: Drive I/O Read B. This signal
is used jointly with IDECS0# and IDECS1#. The falling edge of the
IDEIORB# enables data from the secondary port IDE device. The
data is latched internally on the rising edge of IDEIORB#.
In UltraDMA Read mode: HDMARDYA#. This signal, when
negated, is used as DMARDY# to pause the UltraDMA cycle for
channel B (secondary).
In UltraDMA Write mode: HSTROBEA#. This signal is used as
the STROBE signal. The device (drive) should latch the data on the
rising and falling edges of STROBE.
DMA Request A. This signal is the primary port DMA handshake
from the IDE device. When asserted, it indicates a data transfer is
requested.
DMA Acknowledge A. This is the primary port DMA handshake to
the IDE device. When asserted, it indicates a data transfer can be
executed.
DMA Request B. This is the secondary port DMA handshake from
the IDE device. When asserted, it indicates a data transfer is
requested.
DMA Acknowledge B. This is the secondary port DMA handshake
to the IDE device. When asserted, it indicates a data transfer can be
executed.
Pin Descriptions
18