w83c554f Winbond Electronics Corp America, w83c554f Datasheet - Page 19

• Manufacturer Part Number: w83c554f
• Description: System I/o Controller With Pci Arbiter & Ultradma/33 Ide Controller
• Manufacturer: Winbond Electronics Corp America

W83C554F
WINBOND ELECTRONICS CORP. AMERICA
Pin Name
IDECS0#
IDECS1#/
NAT/LEG#
IDEIOWA#/
STOPA
IDEIORA#/
HDMARDYA#/
HSTROBEA#
Pin #
87
86
85
83
Table 2-4. IDE Interface Bus Signals
Input/
Output
Output
Input/
Output
Output
Output
Description
Drive Chip Select 0. This signal is decoded from the AD bus to
select both primary and secondary IDE Port Command Block
Registers.
Drive Chip Select 1. This signal is decoded from the AD bus to
select both primary and secondary IDE Port Auxiliary Registers.
Native or Legacy Mode Select. During reset, this pin is sampled as
an input to set the Native or Legacy mode of the bus master IDE
controller (Function 1). A high selects Native mode and a low
selects Legacy mode.
Multi-function pin.
In PIO and Multiword DMA modes: Drive I/O Write A. This signal
is used jointly with IDECS0# and IDECS1#. The rising edge of
IDEIOWA# latches data into the primary port IDE device.
In UltraDMA mode: STOPA. This signal is used to terminate an
UltraDMA transaction by 554F.
Multi-function pin.
In PIO and Multiword DMA modes: Drive I/O Read A. This signal
is used jointly with IDECS0# and IDECS1#. The falling edge of
IDEIORA# enables data from the primary port IDE device. The data
is latched internally on the rising edge of IDEIORA#.
In UltraDMA Read mode: HDMARDYA#. This signal, when
negated, is used as DMARDY# to pause the UltraDMA cycle for
channel A (primary).
In UltraDMA Write mode: HSTROBEA#. This signal is used as
the STROBE signal. The device (drive) should latch the data on the
rising and falling edges of STROBE.
Pin Descriptions
17