ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 12

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
DDR1/DDR2 SDRAM Memory Controller
The DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete
devices. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The
DDR2 SDRAM controller interfaces to the PLB through a Memory Queue (MQ) function that includes six high-
speed 1KB FIFO buffers.
Features include:
External Peripheral Bus Controller (EBC)
Features include:
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• PCI-X initialization sequence support (frequency & mode determination)
• Support for unexpected split completions
• Outbound transaction split discard timers
• Vital Product Data (VPD) support
• PCI-X to PCI-Express opaque bridge
• Registered and non-registered industry standard DIMMs
• DDR2 400/667 support
• 64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)
• 5.32GB/s peak bandwidth for the 64-bit interface
• 2.66GB/s peak bandwidth for the 32-bit interface
• Four chip (bank) select signals supporting 4 external banks
• CAS latencies of 2, 3, 4, 5, 6, and 7 supported
• Page mode accesses (up to 32 open pages) with configurable paging policy
• Look-ahead request queue with programmable depth of four commands.
• Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current
• Up to 16GB in four external banks
• Up to 6 MemClkout signals for high loading unbuffered DIMMS
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Sync DRAM configuration by means of mode register and extended mode register set commands
• Power management (self-refresh, suspend, sleep)
• Low Latency & High Bandwidth PLB ports
• Selectable PLB read response (immediate or deferred)
• Programmable Low Latency & High Bandwidth arbitration schemes
• High Bandwidth port has four 1KB read buffers and two 1KB write buffers
• Low Latency port has four 128B read buffers and two 128B write buffers
• Support Boot ROM on Bank 0; programmable size 2, 4, 8,16 MB
• Up to three ROM, EPROM, SRAM, Flash memory, and slave peripherals supported
• Burst and non-burst devices
• 16 or 8-bit data bus
• 27-bit address, 128MB address space for Banks 1 & 2
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device
• Programmable address mapping
bank)
– 256 Wait States for non-burst
– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses
– Programmable CSon, CSoff relative to address
– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
.
Preliminary Data Sheet
Revision 1.23 - Sept 21, 2006
AMCC Proprietary