ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 52

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
Table 6. Signal Functional Description (Sheet 3 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k: to 3.3V
3. Must pull down (recommended value is 1k:)
4. If not used, must pull up (recommended value is 3k: to 3.3V)
5. If not used, must pull down (recommended value is 1k:)
6. Strapping input during reset; pull-up or pull-down required
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PCIX0Req64/PCIX0ECC6
PCIX0Reset
PCIX0SErr
PCIX0Stop
PCIX0TRDY
PCIX0VC
PCIX0VRef0:1
DDR SDRAM Interface
BA0:2
BankSel0:3
CAS
ClkEn0:3
DM0:8
DQS0:8
DQS0:8
ECC0:7
MemAddr14:00
MemClkOut0:5
MemClkOut0:5
MemData63:00
Signal Name
Request 64-bit transfer or ECC6.
Normally used by the current bus master to indicate a
64-bit transfer.
Used as ECC6 for PCIX0 mode 2.
Sets PCI device registers and logic to a consistent state.
Reports address parity errors, data parity errors on the
Special Cycle command, or other catastrophic system
errors.
Indicates the current target is requesting the master to
stop the current transaction.
I
current data phase of the transaction.
Voltage control output. Used to control the voltage
regulator supplying the PCI I/O voltage. See PCIX0Cap
signal.
0 = 3.3V (PCI I/O)
1 =1.5V (PCI-X DDR)
Voltage reference input for PCI-X mode 2/DDR (1.5V)
I/O. Not used for PCI or PCI-X mode 1.
Bank Address supporting up to 8 internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
Clock Enable. One for each external bank.
Memory write data byte lane masks. MEMDM8 is the
byte lane mask for the ECC byte lane.
Byte lane data strobe. DQS8 is the data strobe for the
ECC byte lane. These signals are differential pairs.
ECC check bits 0:7.
Memory address bus.
Note:
Subsystem clocks. The Clock signal (differential pair) is
duplicated six times to support high loading:
Six clocks can be used for two unbuffered DIMMS.
Each individual clock signal can be enabled by
programming the SDR0_DDRCLKSET register.
Memory data bus.
Note:
ndicates the target agent’s ability to complete the
MemAddr14 is the most significant bit (msb).
MemData63 is the most significant bit (msb).
Description
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
Preliminary Data Sheet
I
3.3(1.5)V PCI
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
1.5V PCI for
3.3V PCI or
VPCIXDDR
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
2.5(1.8)V
2.5(1.8)V
2.5(1.8)V
2.5(1.8)V
2.5(1.8)V
2.5(1.8)V
2.5(1.8)V
2.5(1.8)V
2.5(1.8)V
2.5(1.8)V
Revision 1.23 - Sept 21, 2006
mode 2
Type
DIFF
DIFF
Notes
AMCC Proprietary
4
4
4
4
5