ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 75

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ppc440spe

Manufacturer Part Number
ppc440spe
Description
Powerpc 440spe Embedded Processor
Manufacturer
Applied Micro Circuits Corporation (AMCC)
Datasheet

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PowerPC 440SPe Embedded Processor
Table 20. DDR SDRAM I/O Read Timing—T
Notes:
1. T
2. Clock speed for the values in the table is 333.33MHz.
3. The time values in the table include 1/4 of a cycle at 166MHz (3ns x 0.25 = 0.75 ns).
4. To obtain adjusted T
In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a
slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal
routing. It is recommended that the signal length for all of the eight DQS signals be matched.
Figure 10. DDR SDRAM Memory Data and DQS
AMCC Proprietary
MemData00:07
MemData08:15
MemData16:23
MemData24:31
MemData32:39
MemData40:47
MemData48:55
MemData56:63
ECC0:7
of the cycle time for the lower clock frequency (e.g., T
SD
and T
Signal Names
HD
DQS
MemData
are measured under worst case conditions.
SD
and T
T
SD
HD
T
HD
values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4
Reference Signal
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
SD
and T
SD
HD
- 0.75 + 0.25T
Read Data vs DQS Set up
T SD (ns)
CYC
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
).
Preliminary Data Sheet
Revision 1.23 - Sept 21, 2006
Read Data vs DQS Hold
T HD (ns)
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
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