ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 55

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
Table 6. Signal Functional Description (Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k: to 3.3V
3. Must pull down (recommended value is 1k:)
4. If not used, must pull up (recommended value is 3k: to 3.3V)
5. If not used, must pull down (recommended value is 1k:)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
UART Peripheral Interface
UARTSerClk
UART0_Rx
UART0_Tx
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0_RI
UART1_Rx
UART1_Tx
UART1_DSR/CTS
UART1_DTR/RTS
UART2_Rx
UART2_Tx
Interrupts Interface
IRQ0:15
System Interface
Halt
GPIO00:31
SysClk
SysErr
SysPartSel
SysReset
ExtReset
Signal Name
Serial clock input that provides an alternative to the
internally generated serial clock. Used in cases where
the allowable internally generated clock rates are not
satisfactory.
UART0 Receive data.
UART0 Transmit data.
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
UART1 Receive data.
UART1 Transmit data.
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
UART1 Request To Send or Data Terminal Ready. The
choice is determined by a DCR register bit setting.
UART2 Receive data.
UART2 Transmit data.
External interrupt Requests 0 through 15.
These pins are multiplexed with GPIO16:31
Halt from external debugger.
General purpose I/O 0 through 31.
The GPIOs are multiplexed with IRQs, and Trace signal
IO. Setting is done with the DCR register bits.
Main system clock input.
Set to 1 when a machine check is generated.
Not used.
Main system reset. External logic can drive this pin low
(minimum of 16 cycles) to initiate a system reset. A reset
of the PPC440SPe can also be initiated by software.
External Reset. During the PPC440SPe’s reset phase
this signal is at down level.
Description
I/O
I/O
O
O
O
O
O
O
O
O
Preliminary Data Sheet
I
I
I
I
I
I
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Revision 1.23 - Sept 21, 2006
w/pull-up
Type
NA
Notes
1, 4, 6
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 4
1, 5
1, 4
1, 2
4
6
6
4
4
3
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