ppc440spe Applied Micro Circuits Corporation (AMCC), ppc440spe Datasheet - Page 14

• Manufacturer Part Number: ppc440spe
• Description: Powerpc 440spe Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

PowerPC 440SPe Embedded Processor
For more information about the RAID 6 implementation, description, and configuration of the acceleration
hardware, refer to the following AMCC documents:
XOR/DMA2 Controller
The XOR/DMA2 controller performs the XOR functions needed to support RAID 5 applications including parity
generation and check functions used across data stripes in a RAID 5 system.
Serial Port
The serial port is compatible with the NS
Features include:
IIC Bus Interface
Features include:
14
• PowerPC 440SP/440SPe RAID Support Application Note
• PowerPC 440SPe RAID Addendum to the User’s Manual
• Computes a bit-wise XOR on up to 16 data streams with result stored in designated target
• Performs XOR check on up to 16 data streams
• Driven by a linked list Command Block structure specifying control information, source operands, target
• Source and target streams may reside anywhere in PLB address space.
• Provides completion status per Command Block to be handled by software at a later time
• 96-byte and 160-byte Command Block formats are supported
• No memory alignment restrictions on operands or target
• Internal register arrays and data buffers are parity protected
• Can be used as a DMA controller (DMA2) with single source and target addresses
• PLB Master interface
• PLB Slave port used as control interface for reading and writing control and status information
• One 8-pin, one 4-pin, and one 2-pin interfaces are provided
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility with 16750 register set
• Complete status reporting capability
• Fully programmable serial-interface characteristics
• Two IIC interfaces provided
• Support for Philips
• Operation at 100kHz or 400kHz
• 8-bit data
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully programmable configuration registers
• One programmable interrupt request signal
• Full management of all IIC bus protocols
• Programmable error recovery
• Port 0 supports serial Bootstrap ROM with default override parameters at initialization
operand, status information, and link
DD
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Semiconductors I
IIC interface
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2
16570 UART interface.
C Specification, dated 1995
Preliminary Data Sheet
Revision 1.23 - Sept 21, 2006
AMCC Proprietary