u3742bm ATMEL Corporation, u3742bm Datasheet - Page 11

• Manufacturer Part Number: u3742bm
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Basic Clock Cycle of the
Digital Circuitry
4735A–RKE–11/03
The complete timing of the digital circuitry and the analog filtering is derived from one
clock. According to Figure 11, this clock cycle T
(XTO) in combination with a divider. The division factor is controlled by the logical state
at pin MODE. According to section “RF Front End” on page 4, the frequency of the crys-
tal oscillator (f
operating frequency of the local oscillator (f
Figure 11. Generation of the Basic Clock Cycle
Pin MODE can now be set in accordance with the desired clock cycle T
the following application-relevant parameters:
•
•
•
•
•
Most applications are dominated by two transmission frequencies: f
mainly used in the USA, f
T
each parameter.
•
•
•
The clock cycle of some function blocks depends on the selected baud rate range
(BR_Range) which is defined in the OPMODE register. This clock cycle T
by the following formulas for further reference:
BR_Range =
Clk
-dependent parameters, the electrical characteristics display three conditions for
Timing of the polling circuit including bit check
Timing of the analog and digital signal processing
Timing of the register programming
Frequency of the reset marker
IF filter center frequency (f
Application USA (f
Application Europe (f
Other applications (T
The electrical characteristic is given as a function of T
XTO
BR_Range0:
BR_Range1:
BR_Range2:
BR_Range3:
) is defined by the RF input signal (f
XTO
XTO
Clk
Send
= 4.90625 MHz, MODE = L, T
is dependent on f
= 6.76438 MHz, MODE = H, T
:14/:10
Divider
= 433.92 MHz in Europe. In order to ease the usage of all
XTO
IF0
)
T
T
T
T
T
f
XTO
CLK
XClk
XClk
XClk
XClk
= 8 ´ T
= 4 ´ T
= 2 ´ T
= 1 ´ T
16
15
14
DVCC
MODE
XTO
LO
).
XTO
Clk
Clk
Clk
Clk
Clk
and on the logical state of pin MODE.
L : USA(:10)
H: Europe(:14)
is derived from the crystal oscillator
Clk
Clk
RFin
= 2.0383 µs)
Clk
).
) which also defines the
= 2.0697 µs)
U3742BM
Send
Clk
= 315 MHz is
XClk
. T
Clk
is defined
controls
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