u3742bm ATMEL Corporation, u3742bm Datasheet - Page 12

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u3742bm

Manufacturer Part Number
u3742bm
Description
Uhf Ask/fsk Receiver
Manufacturer
ATMEL Corporation
Datasheet

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Polling Mode
Sleep Mode
12
U3742BM
According to Figure 13 on page 14, the receiver stays in polling mode in a continuous
cycle of three different modes. In sleep mode, the signal processing circuitry is disabled
for the time period T
period, T
check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter
signal. If no valid signal is present, the receiver is set back to sleep mode after the
period T
age value for T
the current consumption is I
dependent on the duty cycle of the active mode and can be calculated as:
During T
tee the reception of a transmitted command, the transmitter must start the telegram with
an adequate preburst. The required length of the preburst is dependent on the polling
parameters T
(T
(N
The following formula indicates how to calculate the preburst length.
T
The length of period T
the extension factor X
T
T
In US- and European applications, the maximum value of T
is set to 1. The time resolution is about 2 ms in that case. The sleep time can be
extended to almost half a second by setting X
XSleep
below:
XSleep
XSleep
as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 auto-
matically resulting in a regular sleep time. This functionality can be used to save current
in the presence of a modulated disturber similar to an expected transmitter signal. The
connected microcontroller is rarely activated in that condition. If the disturber disap-
pears, the receiver switches back to regular polling and is again sensitive to appropriate
transmitter signals.
According to Table 7 on page 21, the highest register value of Sleep sets the receiver
into a permanent sleep condition. The receiver remains in that condition until another
value for Sleep is programmed into the OPMODE register. This function is desirable
where several devices share a single data line.
I
Spoll
Preburst
Clk
Sleep
Start,microcontroller
Bitcheck
. It is calculated to be:
=
= Sleep ´ X
Std
Temp
I
----------------------------------------------------------------------------------------------------------
Std
³ T
Soff
Bitcheck
) to be tested.
Sleep
Startup
= 1 implies the standard extension factor. The sleep time is always extended.
or by bit XSleep
Sleep
´
= 1 implies the temporary extension factor. The extended sleep time is used
T
and T
Sleep
T
, all signal processing circuits are enabled and settled. In the following bit
. This period varies check by check as it is a statistical process. An aver-
Sleep
Bitcheck
Sleep
+ T
). T
, T
Sleep
+
Startup
Startup
+
Startup
Bitcheck
I
Sleep
Son
T
is given in the electrical characteristics. During T
Sleep
Sleep
´ 1024 ´ T
Startup
, the receiver is not sensitive to a transmitter signal. To guaran-
´
+ T
, T
while consuming low current of I
(
, according to Table 8 on page 21, and the basic clock cycle
T
thus depends on the actual bit rate and the number of bits
is defined by the 5-bit word Sleep of the OPMODE register,
S
Temp
Bitcheck
Startup
+
Bitcheck
= I
T
Bitcheck
Son
Clk
resulting in a different mode of action as described
+
. The average current consumption in polling mode is
+ T
and the startup time of a connected microcontroller
T
Bitcheck
Start_microcontroller
)
Sleep
to 8. X
S
Sleep
Sleep
= I
Soff
is about 60 ms if X
can be set to 8 by bit
. During the start-up
Startup
4735A–RKE–11/03
and T
Bitcheck
Sleep

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