u3742bm ATMEL Corporation, u3742bm Datasheet - Page 13

• Manufacturer Part Number: u3742bm
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Bit Check Mode
Configuring the Bit Check
4735A–RKE–11/03
In bit check mode, the incoming data stream is examined to distinguish between a valid
signal from a corresponding transmitter and signals due to noise. This is done by subse-
quent time frame checks where the distances between 2 signal edges are continuously
compared to a programmable time window. The maximum count of these edge-to-edge
tests, before the receiver switches to receiving mode, is also programmable.
Assuming a modulation scheme that contains 2 edges per bit, two time frame checks
are verifying one bit. This is valid for Manchester, bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable N
checks respectively. If N
switch to receiving mode due to noise. In the presence of a valid transmitter signal, the
bit check takes less time if N
time is not dependent on N
are tested successfully and the data signal is transferred to pin DATA.
According to Figure 12, the time window for the bit check is defined by two separate
time limits. If the edge-to-edge time t
the upper bit check limit T
T
switches to sleep mode.
Figure 12. Valid Time Window for Bit Check
For best noise immunity it is recommended to use a low span between T
T
preburst. A '11111...' or a '10101...' sequence in Manchester or bi-phase is a good
choice concerning that advice. A good compromise between receiver sensitivity and
susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge
time t
check limits must be programmed according to the required span.
The bit check limits are determined by means of the formula below:
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the
required T
T
according to the section “Receiving Mode” on page 16. Due to this, the lower limit
should be set to Lim_min ³ 10. The maximum value of the upper limit is Lim_max = 63.
Lim_min
Lim_max
Lim_min
Lim_max
Lim_max
ee
. Using preburst patterns that contain various edge-to-edge time periods, the bit
. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter
= Lim_min ´ T
= (Lim_max - 1) ´ T
is T
or t
Bitcheck
Lim_min
XClk
ee
exceeds T
. The minimum edge-to-edge time t
, T
in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge
Dem_out
Lim_max
XClk
Bitcheck
Lim_max
Bitcheck
and T
Lim_max
XClk
Bitcheck
. Figure 11 on page 11 shows an example where 3 bits
is set to a higher value, the receiver is less likely to
, the bit check will be terminated and the receiver
XClk
T
T
, the check will be continued. If t
Lim_min
is set to a lower value. In polling mode, the bit check
Lim_max
ee
t
ee
. The time resolution when defining T
is in between the lower bit check limit T
1/f
Sig
ee
(t
DATA_L_min
, t
DATA_H_min
U3742BM
ee
is smaller than
) is defined
Lim_min
Lim_min
Lim_min
and
and
and
13