u3742bm ATMEL Corporation, u3742bm Datasheet - Page 17

• Manufacturer Part Number: u3742bm
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Figure 18. Synchronization of the Demodulator Output
Figure 19. Debouncing of the Demodulator Output
Figure 20. Steady L State Limited DATA Output Pattern after Transmission
4735A–RKE–11/03
Dem_out
DATA
Counter
Dem_out
DATA
Bit check
Clock bit check
Enable IC
Dem_out
DATA
Startup mode
Lim_min ≤ CV_Lim < Lim_max
T
XClk
t
ee
The minimum time period between two edges of the data signal is limited to
t
same time, it limits the maximum frequency of edges at DATA. This eases the interrupt
handling of a connected microcontroller. T
ceding edge-to-edge time interval tee as illustrated in Figure 19. If t
specified bit check limits, the following level is frozen for the time period
T
the relevant stable time period.
The maximum time period for DATA to be Low is limited to T
ensures a finite response time during programming or switching off the receiver via pin
DATA. T
transmitter data stream. Figure 20 gives an example where Dem_out remains Low after
the receiver is in receiving mode.
ee
DATA_min
³ T
Bit check mode
DATA_min
DATA_L_max
= tmin1, in case of t
. This implies an efficient suppression of spikes at the DATA output. At the
t
CV_Lim < Lim_min or CV_Lim ≥ Lim_max
ee
tmin1
is thereby longer than the maximum time period indicated by the
Receiving mode
t
ee
ee
being outside that bit check limits T
DATA_min
tmin2
is to some extent affected by the pre-
tmin2
t
DATA_L_max
DATA_L_max
ee
DATA_min
U3742BM
is in between the
. This function
= tmin2 is
17