u3742bm ATMEL Corporation, u3742bm Datasheet - Page 16

• Manufacturer Part Number: u3742bm
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Figure 17. Timing Diagram for Failed Bit Check (Condition: CV_Lim ³ Lim_max)
Duration of the Bit Check
Receiving Mode
Digital Signal Processing
16
Enable IC
Bit check
Dem_out
Bit check counter
(Lim_min = 14, Lim_max = 24)
U3742BM
Startup mode
0
Figure 15 to Figure 17 illustrate the bit check for the default bit check limits
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits
are enabled during T
fined during that period. When the bit check becomes active, the bit check counter is
clocked with the cycle T
Figure 15 on page 15 shows how the bit check proceeds if the bit check counter value
CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a sig-
nal edge. In Figure 16 on page 15, the bit check fails as the value CV_lim is lower than
the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated
in Figure 17.
If no transmitter signal is present during the bit check, the output of the ASK/FSK
demodulator delivers random signals. The bit check is a statistical process and T
varies for each check. Therefore, an average value for T
characteristics. T
baud rate range causes a lower value for T
tion in polling mode.
In the presence of a valid transmitter signal, T
that signal, f
thereby results in a longer period for T
preburst T
If the bit check has been successful for all bits specified by N
switches to receiving mode. According to Figure 14, the internal data signal is switched
to pin DATA in that case. A connected microcontroller can be woken up by the negative
edge at pin DATA. The receiver stays in that condition until it is switched back to polling
mode explicitly.
The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different
ways and as a result converted into the output signal data. This processing depends on
the selected baud rate range (BR_Range). Figure 18 on page 17 illustrates how
Dem_out is synchronized by the extended clock cycle T
the bit check counter. Data can change its state only after T
edge-to-edge time period t
of T
1
2 3 4 5 6
XClk
.
Preburst
7
Sig
1
2
and the count of the checked bits, N
.
3
Bitcheck
4 5
Bit check mode
Startup
6 7 8 9
XClk
depends on the selected baud rate range and on T
. The output of the ASK/FSK demodulator (Dem_out) is unde-
ee
.
10
of the Data signal as a result is always an integral multiple
1/2 Bit
1112
13141516171819
Bitcheck
Bitcheck
requiring a higher value for the transmitter
Bit check failed (CV_Lim ≥ Lim_max)
20
Bitcheck
21222324
resulting in a lower current consump-
Bitcheck
is dependant on the frequency of
XClk
Bitcheck
. A higher value for N
. This clock is also used for
Sleep mode
is given in the electrical
0
Bitcheck
XClk
elapsed. The
, the receiver
4735A–RKE–11/03
Clk
. A higher
Bitcheck
Bitcheck