cx29610 Mindspeed Technologies, cx29610 Datasheet - Page 71

• Manufacturer Part Number: cx29610
• Description: Optiphytm - M622 Sts-12/4x Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

CX29610
CX29610 Data Sheet
Table 2-14. DCC Transmit Values
29610-DSH-001-C
EnTxSecDCC (bit 6)
2.4.2.7 D1-D3
0
0
1
1
2.4.2.4 B1
2.4.2.5 E1
2.4.2.6 F1
TXSEC Register
SecDCCSrc (bit 5)
The B1 octets are allocated for section layer monitoring and contain a Bit
Interleaved Parity (BIP-8) code. An error causes the B1Err bit in RXSEC to be set
high and increments the B1CNT registers.
The transmit value can be forced to 00 by setting DisB1, bit 2 of the TXSEC
register.
register. This performs an XOR between the B1 octet (either the valid BIP-8
value or 00, depending on DisB1) and the contents of the ERRPAT register and
transmits the result.
The Section Orderwire byte, E1, is allocated as an orderwire channel for voice
communication. It is set to 00h as the default. If TXSEC bit 0 is set high, E1 will
contain data as shifted in from the TxE1 input pin.
output pin. See
The Section User’s Data Channel byte, F1, is allocated for the user. It contains the
value in the TXF1 register.
maskable interrupt (SECINT bit 0) is generated when the incoming F1 byte
differs from the current value for 3 consecutive frames.
The Section Data Communication Channels (SDCC), D1–D3, provides for the
transmission of management and status information. On the receive side, the
D1/D2/D3 octet values are latched from the incoming data stream and output on
both the SI-Bus and the RxSDCC_D pins.
SI-Bus port 0.
0
1
0
1
On the transmit side, the B1 octet contains the BIP-8 calculation by default.
A BIP error can be introduced by setting InsB1Err, bit 6 of the ERRINS
The E1 byte is latched from receive stream and then shifted out to the RxE1
The F1 byte is latched in to the RXF1 register for processor access. A
The transmit values are determined as shown in
In OC-12 mode, the DCC transmit values are sourced from TxSDCC_D[0] or
Mindspeed Technologies
Section 5.1.6
All zeroes
All zeroes
Data input on the TxSDCC_D pin
Data from the SI-Bus
for timing waveforms.
Transmit Source for D1, D2, and D3
2.4 SONET/SDH Framer and Overhead Processor
™
Table
2.0 Functional Description
2-14:
2-27