cx29610 Mindspeed Technologies, cx29610 Datasheet - Page 79

• Manufacturer Part Number: cx29610
• Description: Optiphytm - M622 Sts-12/4x Sts-3 Sonet/sdh Multiplexer
• Manufacturer: Mindspeed Technologies

CX29610
CX29610 Data Sheet
29610-DSH-001-C
2.4.4.4 G1
2.4.4.3 C2
The Path Signal label byte, C2, identifies the type of payload being received. C2
carries the value from the SI-Bus as the default. If PTHINSL bit 5 is high, then
C2 will contain the contents as received on the SI-Bus interface.
received for 5 consecutive frames. The received value is compared to the
provisioned value programmed into the PROVC2 register to monitor for PLM-P
and Uneq-P alarms. PLM-P and Uneq-P are reported in RXPTH bits 2 and 1,
respectively.
received C2 value indicates a different payload specific functionality than that
provisioned in the PROVC2 register. PLM-P is terminated upon detection of
Uneq-P.
value indicates unequipped (00h) and the PROVC2 register contains an equipped
functionality code.
The Path Status byte, G1, is used to convey path terminating status and
performance monitoring information back to an originating STS PTE. Errors are
reported in RXPTH bit 3 and counted in RPCNT. The counter length is 16 bits so
that saturation does not occur during a one-second latching interval. G1 is also
monitored for RDI-P errors. RDI-P errors are reported in RXPTH bit 5. G1
contains the REI-P and RDI-P values in response to incoming B3 BIP errors and
path alarms as the default. If TXPTH bit 5 is low, G1 bits 1–4 will contain 0000.
If PTHINSH bit 2 is written high, the contents of the ERRPAT bits 7–4 will be
transmitted in G1 bits 1–4 for one frame. If PTHINSL bit 4 is high, then G1 will
contain the contents as received on the SI-Bus interface regardless of the settings
of other control bits affecting G1.
table. The RDI bits from the G1 byte are latched into the RXRDI register when a
consistent new value is received for 10 consecutive frames.
Table 2-21. G1 bit Interpretation
generation is the default (TXPTH bit 0 high). G1 bits 5, 6, 7 contain the RDI-P
indications; the contents are shown in the table below in order of generation
priority.
or RDI-P (101 or 110).
The C2 byte is latched into the RXC2 register after consistent values are
Payload Label Mismatch (PLM-P) is reported in RXPTH bit 2 when the
Path Unequipped (Uneq-P) is reported in RXPTH bit 1 when the received C2
Path RDI (RDI-P) is reported in RXPTH bit 5 according to the following
RDI-P can be generated either automatically or manually. Automatic
REI-P counts are disabled during LOS, LOF, AIS-L, AIS-P, LOP-P, Uneq-P,
G1 bits 5, 6, 7
000, 011, 001
Mindspeed Technologies
100, 111
010
101
110
No RDI-P defect
One-bit RDI-P defect
ERDI-P payload defect
ERDI-P server defect
ERDI-P connectivity defect
2.4 SONET/SDH Framer and Overhead Processor
™
Interpretation
2.0 Functional Description
2-35