cx29503 Mindspeed Technologies, cx29503 Datasheet - Page 352

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cx29503

Manufacturer Part Number
cx29503
Description
Cx29503 Broadband Access Multiplexer Data Sheet
Manufacturer
Mindspeed Technologies
Datasheet
Register Description
Table 8-61. CSP Control Registers <tableContinuation>(2 of 2)
8-222
FOOTNOTE:
(1)
Offset (Hex)
802B–803F
8800–8FFF
9000–9FFF
Writeable only by Host-through-Parallel Interface
801B
801C
801D
801E
8020
8021
8022
8023
8024
8025
8026
8027
8028
8029
802A
801F
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Clear on
Partial
Read
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Mindspeed Technologies™
Interrupt 6 (TSB) Source Priority Level
Period Compare Register Low Byte
Period Compare Mid-Low Byte
Period Compare Mid-High Byte
Period Compare High Byte
HDLC Controller Status (Read-Clear)
HDLC Transmit Message Length FIFO
HDLC Received Message Length FIFO
Parallel Interface Control (DTACK Deassertion Time)
CSP Memory Offset Register
Tickle Pattern (Low Byte)
Tickle Pattern (High Byte)
Time-out Period (Low Byte)
Time-out Period (Mid-Low Byte)
Time-out Period (Mid-High Byte)
Time-out Period (High Byte)
Reserved
Data RAM (Scratchpad)
Program RAM
Preliminary Information
Register Description
Value After Reset
CX29503 Data Sheet
29503-DSH-002-B
(Hex)
0x00
0x00
0x00
0x00
0x03
0x00
0x00
0x00
0x00
0x14
0x73
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0x0F

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