cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 33

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
Table 1-2. Hardware Signal Definitions (4 of 5)
100046D
SEL8BIT
PRCLK
CS~
AS~
W/R~
OE~
DL_INT
STAT_INT
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
Pin Label
8/16 Bit Mode
Select
Processor Clock
Chip Select
Address Strobe
Write/Read Control
Output Enable
FEAC/HDLC
Interrupt
Status/Counter
Interrupt
Processor Data
Bus
Signal Name
No.
37
97
96
94
95
92
63
64
65
68
69
70
71
72
73
74
75
76
77
78
79
82
83
84
Conexant
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
CMOS/TTL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I
I
If asserted, this pin selects an 8-bit
microprocessor bus. If not asserted, it selects a
16-bit bus.
Clock input to the microprocessor interface. All
inputs are synchronous to this clock except OE~.
All read and write operations require two cycles
of PRCLK. PRCLK must run continuously at a
minimum frequency of 2 times the cell rate.
Must be logic low to address chip. Must be low
to enable a read or write operation and should
be stable throughout the cycle.
If this pin is low, a new address is loaded on the
rising edge of PRCLK for the operation in the
following clock period. If this pin is high and
CS~ is low, a read or a write operation is
executed. The address strobe can stay low for
multiple clock periods. Address strobe cannot
stay high with CS~ low for multiple clock
periods.
If this pin is low when CS~ is low, the following
cycle is a read operation. If this signal is high
when CS~ is low, the data presented at the end
of the following clock cycle will be written if CS~
is still low on that cycle.
This signal must be low to enable the data
output for a read cycle. Data bus outputs are
three-stated if this signal is high. The data is
valid between clock edges on a read cycle when
this pin is low. This pin may be connected
directly to ground, if desired.
Active-low data link channel interrupt output
with open drain.
Active-low status/counter interrupt with open
drain.
This signal is a 16-bit bidirectional data bus for
read and write data.
Definition
1.0 Product Description
1.10 Pin Definitions
1-23