cn8223 Mindspeed Technologies, cn8223 Datasheet - Page 67

• Manufacturer Part Number: cn8223
• Description: Atm Transmitter/receiver With Utopia Interface
• Manufacturer: Mindspeed Technologies

CN8223
ATM Transmitter/Receiver with UTOPIA Interface
2.6.3 PLCP Cell Generation for Transmit
100046D
interrupt, it rolls over to zero, sets the interrupt, and continues counting errors
after it reaches its maximum value. If a counter is not set to interrupt, it saturates
and holds when it reaches its maximum value (0xfff). The interrupt enable bits for
the counters are found in the EN_CELL_INT register [0x30], with the
corresponding interrupt status in the CELL_STATUS register [0x38]. If one of
the cell counter overflow interrupts occurs, the CELL_STATUS register can be
read to determine which counter or counters overflowed. These interrupts are
cleared when CELL_STATUS is read.
transmission/reception of individual cells. These interrupts may be enabled in
EN_CELL_INT with corresponding status bits in CELL_STATUS. Cell
Rcvd—Port x indicates the validation process has received a complete ATM cell
destined for Port x. Cell Sent—Port x indicates a cell has been transmitted from
source x. These interrupts are cleared when CELL_STATUS is read.
In 57-octet PLCP formats, the PLCP overhead generation consists of the framing
octets A1 and A2, the Path Overhead Identifier (POI) octets, and the path
overhead octets. All of these are generated by the PHY transmit circuitry, but can
be selectively disabled if desired.
octets are determined by the particular PLCP that is selected, but in each case they
consist of a slot count and a parity bit. The DS3 PLCP has 12 slots per frame, the
DS1 and E1 PLCP have 10, and the E3 PLCP has 9. In each case, the POI octets
provide a backwards count of the PLCP slots in the frame, along with a parity bit.
Generation of the A1, A2, and POI octets can be disabled via the Overhead
Control [bits 3–0] of CONFIG_2 [0x01]. All path overhead growth octets Zn and
the path user channel F1 are forced to zero.
frame. The BIP Error Insert [bits 12–10] of CONFIG_2 control insertion of BIP-8
errors in the generated PLCP. If errors are to be inserted, a non-zero value written
to the TXFEAC_ERRPAT register inverts the corresponding bits of the B1 octet
from that calculated by the BIP-8 circuit in the following PLCP frame. Insert
control bits are cleared after each frame when the errors are inserted. The register
can be read to determine if this has occurred, so that the microprocessor can insert
BIP-8 errors as desired in each PLCP frame.
Counter overflow interrupts can be individually enabled. If a counter is set to
Some interrupts in the CELL_STATUS register are related to the
The A1 and A2 octets are generated according to TR-TSV-000773. The POI
The B1 octet is populated with a BIP-8 code that is calculated over each PLCP
Conexant
2.0 Functional Description
2.6 ATM Cell Processing
2-33