cx28365 Mindspeed Technologies, cx28365 Datasheet - Page 76

• Manufacturer Part Number: cx28365
• Description: X12, X6, X4 T3/e3 Framer And Atm Cell Transmission Convergence Sublayer Processor
• Manufacturer: Mindspeed Technologies

Functional Description
2.1.2.5
2-38
If the ExtFEBE/Cj field in the TransmitOverheadInsertion1 Control register is enabled,
REI is transmitted on the transmit stream upon a PER event in E3-G.832 mode.
Path Parity Error (PPER)
In DS3 C-bit parity mode, the PPER event is declared when at least two of the three
Cb3 bits differ in value from the expected value as calculated from the previous frame.
The PPER event increments the PPER counter.
If the ExtFEBE/Cj field of the TransmitOverheadInsertion 1 Control register is
enabled, FEBE is transmitted on the transmit stream upon a PPER event.
Remote Alarm/Defect Indication (RAI/RDI), X-bit disagreement (XBD)
In DS3, an RAI/RDI event is declared when both X-bits of a receive frame are 0. The
RAI/RDI event is terminated when both X-bits are 1. The XBD event is declared
when the two X-bits are not equal.
In E3, an RAI/RDI event is declared when two consecutive receive frames have an A/
RDI bit with the value 1. The RAI/RDI event is terminated when two consecutive
frames have an A/RDI bit with the value 0. The XBD event is not defined.
The RAI/RDI also generates a YelStrt interrupt indication and sets the YelDet status
indication bit in the Maintenance Status register. Upon terminating, the RAI/RDI
event generates a YelEnd interrupt indication and clears the YelDet status indication
bit. The XBD event increments the XBD counter.
Far-End Block Error/Remote Error Indication (FEBE/REI)
The FEBE/REI event is defined only in DS3 C-bit parity mode and E3-G.832 mode.
In DS3 C-bit parity mode, it is declared when at least one of the three Cb4 bits is 0. In
E3-G.832 mode, it is declared when the REI-bit is 1. The FEBE/REI event increments
the FEBE/REI counter.
Terminal Data Link Reception
The terminal data link channel (DL) resides on the C5 bits of DS3 C-bit Parity frames,
which is approximately 28.195 Kbps (3/4760 bits at 44.736 Mbps). On the N-bit of
E3-G.751 frames, it is approximately 22.375 Kbps (1/1536 bits at 34.368 Mbps). On
the NR or GC (but not both) bytes of E3-G.832 frames, it is approximately 64 Kbps
(1/537 bytes at 34.368 Mbps). The DL contents are generally available via one or
more of three routes the data stream (marked with other overheads by RxGCKO),
marked by REXTCKO, or through a FIFO-buffered microprocessor interface the first
two are specified in
mode.
The internal circuitry [Receive Data Link (RDL) block] provides logic and FIFO
buffering for implementing LAPD/HDLC terminal data link reception according to
ITU-T Q.921 and ISO/IEC 3309 standards. The logic is responsible for flag and abort
sequence detection, 16-bit frame check sequence (FCS) checking and transparency
zero removal, and managing the internal FIFO buffer. Each channel contains a
128-byte Receive Data Link FIFO buffer, distinct from the Transmit Data Link FIFO
buffer, to reduce the amount of intervention required from the system in accessing the
data link contents. The FIFO buffer contents are accessed via the microprocessor
Preliminary Information/Mindspeed Proprietary and Confidential
Mindspeed Technologies™
Section
2.1.2.3; this section describes the details of the third
CX28365/6/4 Data Sheet
500028C