cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 104

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Figure 6-1.
6.4
The Global Configuration Descriptor specifies configuration information applying to the entire device. This register
must be programmed before any channel is activated. The only two fields in this register that can be changed while
the chip is operating (i.e., not immediately after reset) are the INTRS field and the PCI_EN field.
The components and their descriptors are given in
Table 6-20.
28500-DSH-002-C
31:15
14
13
Bit
Field Name
PCHMODE
ECCMODE
Interrupt Notification to Host
Global Configuration Descriptor (1 of 2)
RSVD
Global Configuration Register
Value
0
0
1
0
Unserviced Interrupt
Descriptors in the
Interrupt Queue
Internal Logic
CX28500
Reserved
Normal operating mode (i.e., not Preserve Channel Mode)
Preserve Channel Mode. In this mode requires ECCMODE = 1:
Note that PCHMODE can be set only when ECCMODE bit is set. Doing otherwise causes unpredictable
behavior.
Normal operating mode (i.e., not ECCMODE)
1.
2.
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CX28500 transfers in the Rx direction the channel number least significant 8 bits in bits
[25:8] in the first dword at Status Buffer Descriptor and the channel most significant 2 bits
in bits 1:0 of the second dword of the Status Buffer Descriptor (i.e., the data pointer).
In the Tx direction, CX28500 assumes that the field PADCOUNT in the Buffer Descriptor is 0.
This enables the Host to write any value that helps to better handle buffers circulation into
this location knowing that CX28500 does not use PADCOUNT and preserve this value in the
Status Buffer Descriptor.
INTA*
Table
6-20.
®
Description
Interrupt
Interrupt
Memory
Handler
Queue
Host
Memory Organization
500052_056
89