cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 50

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

Table 1-8.
28500-DSH-002-C
FOOTNOTE:
(1)
(2)
(3)
(4)
(5)
(6)
While operating in TSBUS mode, there is no damage expected when sampling STBx twice, since the RCLKx and TCLKx are the same
signals for a specific port. However, this may require some additional restrictions for the board designers when these clocks are routed.
This signal is used either as Receiver Out-Of-Frame or a Transmit Clear to Send or a TSBUS strobe. (OOF/FREC behavior selected by
OOFABT = 1, CTS behavior selected by CTSENB = 1, STB behavior selected by TPORT_TYPE or RPORT_TYPE.) See related bit fields
configuration (i.e., RSIU Port Configuration Register and TSIU Port Configuration Register). ROOF/CTS/STB/SPORT signals are from the
same pin.
If the serial port operates in conventional mode, then this signal is used either as a ROOFx or CTSx signal.
If the port operates channelized TSBUS mode, then the signal is used as the TSBUS strobe signal, which indicates the beginning of the
TSBUS frame.
Only one pin in the device defines all these functions.
The address line A31 must be asserted in all transactions.
No Connect
Pin Label
VDD_io
VDD_c
TRST*
TM[0]
TM[1]
TM[2]
TMS
GND
TDO
VGG
TCK
TDI
CX28500 Hardware Signal Definitions (7 of 7)
JTAG Mode Select
JTAG Data Output
JTAG Data Input
Input Tolerance
Signal Name
JTAG Enable
No Connect
JTAG Clock
Test Mode
Ground
Power
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Mindspeed Technologies
t/s O
I/O
—
—
—
—
I
I
I
I
I
Used to clock in the TDI and TMS signals and as clock out TDO signal.
An active-low input used to put the chip into a special test mode. This pin
should be pulled low in normal operation.
The test signal input decoded by the TAP controller to control test
operations.
The test signal used to transmit serial test instructions and test data.
The test signal used to receive serial test instructions and test data.
Test modes, reserved for manufacturer testing. Must be tied low for
normal operation.
VDD_c is power supply for internal logics. VDD_io is power supply for
input and output.
ESD diode clamp supply for 5 volts tolerant input where VGG = 5 volts,
otherwise VGG = VDDi = VDDo = 3.3 volts.
Ground pins for internal logics, input, and output are connected to a
common ground.
These pins have no connection. They are reserved for future revisions.
®
Definition
Introduction
35