cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 135

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

The effects of a PCI reset signal within CX28500 takes ten PCI clock cycles to complete after deasserting the reset
signal. After this time, the Host can communicate with CX28500 using the PCI configuration cycles.
After the PCI configuration, the device is not ready to start communication with the Host via service request
mechanism until the SRQ_LEN bit field in Service Request register is set to 0.
7.1.1.2
A soft chip reset is a device-wide reset without the Host interface’s PCI state being reset. Serial interface
operations and EBUS operations are halted. The soft chip reset state is entered in one of two ways:
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A soft chip reset causes the following:
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The Host acts as if this was a PCI reset, except that the PCI configuration does not need to be repeated (it is kept
unchanged).
The Host can assume that the reset was completed by CX28500 and can start configuration of registers when the
field SRQ_LEN is zero. After any kind of reset, the user must reconfigure all aspects of CX28500.
7.1.2
A sequence of hierarchical initialization must occur after resets. The levels of hierarchy are as follows:
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Channel and port configuration involves programming many registers and must be done to comply with its own
hierarchy, as explained below.
7.1.2.1
After power-up or a PCI reset sequence, CX28500 enters a holding pattern. It waits for PCI configuration cycles
directed specifically for CX28500. They are actually directed at the PCI bus and PCI slot where CX28500 resides.
PCI configuration involves PCI read and write cycles. These cycles are initiated by the Host and performed by a
Host-bus-to-PCI-bus bridge device. The cycles are executed at the hardware signal level by the bridge device. The
bridge device polls all possible slots on the bus it controls for a PCI device and then iteratively reads the
configuration space for all supported functions on each device. All information from the basic configuration
sequence is forwarded to the system controller or Host processor controlling the bridge device.
During PCI configuration, the Host can perform the following configuration for CX28500:
28500-DSH-002-C
As a result of the PCI reset
As a result of a soft chip reset Host Service request
Transmit data signals, TDAT, to be three-stated
All EBUS address lines to be three-stated and read enable and write enable outputs to be deasserted, halting
all memory operations on EBUS
All active channels to enter the channel deactivated state
DMA controllers to be reset, halting all PCI transactions
All registers reset to default values
PCI Configuration—only after hardware reset
Interrupt Queue Configuration
Global Configuration
Channel and Port Configuration
Soft Chip Reset
Configuration
PCI Configuration
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Functional Description
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