k4x56163p-lg Samsung Semiconductor, Inc., k4x56163p-lg Datasheet - Page 17

• Manufacturer Part Number: k4x56163p-lg
• Description: 16mx16 Mobile Ddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4X56163PI - L(F)E/G
NOTE :
1) OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
3) Auto refresh functions are same as the CBR refresh of DRAM.
4) BA0 ~ BA1 : Bank select addresses.
7) Burst stop command is valid at every burst length.
19. Command Truth Table
2) EMRS/ MRS can be issued only at all banks precharge state.
5) If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6) During burst write with auto precharge, new read/write command can not be issued.
8) DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9) This combination is not defined for any function, which means "No Operation(NOP)" in Mobile DDR SDRAM.
Column Address
Column Address
A new command can be issued 2 clock cycles after EMRS or MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
Precharge Power Down
Precharge
Register
Refresh
Read &
Write &
No operation (NOP) : Not defined
Active Power Down
Deep Power Down
Bank Active & Row Addr.
Command
Burst Stop
Auto Precharge Disable
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Enable
DM
Refresh
Mode Register Set
Self
Bank Selection
Auto Refresh
All Banks
Entry
Entry
Entry
Entry
Exit
Exit
Exit
Exit
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
CKEn
X
H
H
X
X
X
H
X
X
H
H
X
L
L
L
L
CS
H
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
- 20 -
RAS
H
H
H
H
H
H
L
X
L
X
H
X
V
X
X
X
V
X
L
L
X
CAS
H
X
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
WE
H
H
H
H
H
H
L
X
L
L
X
L
L
X
V
X
X
X
V
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
BA0,1
V
V
V
V
X
Mobile DDR SDRAM
A10/AP
OP CODE
H
H
H
L
L
L
Row Address
X
X
X
X
X
X
X
X
A12,A11,
(A0~A8)
(A0~A8)
Address
Address
Column
Column
A9~A0
X
October 2007
Note
1, 2
4, 6
3
3
3
3
4
4
4
7
5
8
9
9