mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 118

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
0 – No fatal error detected.
3.2.3.6.7
Address 0x10
Reset
This register holds the interrupt flags related to the startup procedure. All flags are read/write for the host.
Each flag has an associated interrupt enable flag in the startup interrupt enable register (see
Section 3.2.3.5.1, “Startup Interrupt Enable Register
reset or when leaving the configuration state.
The host clears a status bit in the SISR by writing a '1' to it. Writing a ‘0’ does not change the bit state. The
CC sets a status bit in the SISR again when it detects the condition for that bit. If the host and the CC try
to access the SISR register at the same time, the CC operation has the higher priority.
CDSTMIF — Coldstart Max Interrupt Flag
This error signal is set if the maximum number of allowed retries of a coldstarting CC (CSMR
programmed value – see
if the CSMR register is programmed with the value N, the CC sets the CDSTMIF bit after the Nth retry
has failed. If enabled, an interrupt remains pending while this flag is set.
1 – Coldstart Maximum value has been reached.
0 – Coldstart Maximum value has not been reached.
PLFIF — Plausibility Failed Interrupt Flag
This error signal is set if the consistency check of the local CC within the startup sequence failed, i.e. the
number of received valid startup frames is less than required. If enabled, an interrupt remains pending
while this flag is set.
1 – A Plausibility Check of the local CC within the startup sequence failed.
0 – A Plausibility Check of the local CC within the startup sequence did not fail.
118
Reserved
Reserved
15
7
r
r
0x0
Startup Interrupt Status Register (SISR)
Reserved
Reserved
14
6
r
r
Section 3.2.3.3.26, “Coldstart Maximum Register
Reserved
Reserved
Figure 3-79. Startup Interrupt Status Register
13
5
r
r
MFR4200 Data Sheet, Rev. 0
Reserved
Reserved
12
4
r
r
(SIER)”). The SISR register is cleared during a hard
CDSTPNSIF
Reserved
rwh
11
3
r
CDSTPNIF
Reserved
rwh
10
2
r
(CSMR)”) is reached. That is,
Reserved
PLFIF
Freescale Semiconductor
rwh
9
1
r
CDSTMIF
Reserved
rwh
8
0
r