January 1996
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
• Dose Rate Survivability . . . . . . . . . . . >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
• Input Current
• Fast Propagation Delay . . . . . . . . . . . . . . . . 15ns (Max), 10ns (Typ)
Description
The Intersil ACS125MS is a Radiation Hardened Quad Buffer with
Three-State outputs. Each output has it’s own enable input, which when
“HIGH” puts the output in a high impedance state.
The ACS125MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACS125MS is supplied in a 14 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
Ordering Information
5962F9670501VCC
5962F9670501VXC
ACS125D/Sample
ACS125K/Sample
ACS125HMSR
SMD# 5962-96705 and Intersil’s QM Plan
(Typ)
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
PART NUMBER
1 A at VOL, VOH
TEMPERATURE RANGE
-55
-55
o
o
C to +125
C to +125
25
25
25
o
o
o
C
C
C
11
12
o
o
C
C
RAD (Si)/s, 20ns Pulse
RAD (Si)/s, 20ns Pulse
-10
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
Errors/Bit/Day
o
C to +125
1
SCREENING LEVEL
2
/mg
o
C
ACS125MS
Pinouts
GND
OE1
OE2
MIL-STD-1835 DESIGNATOR, CDIP2-T14,
MIL-STD-1835 DESIGNATOR, CDFP3-F14
A1
Y1
A2
Y2
14 PIN CERAMIC DUAL-IN-LINE
Quad Buffer, Three-State
GND
14 PIN CERAMIC FLATPACK
OE1
OE2
A1
A2
Y1
Y2
1
2
3
4
5
6
7
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
LEAD FINISH C
LEAD FINISH C
Radiation Hardened
1
2
3
4
5
6
7
TOP VIEW
TOP VIEW
Spec Number
PACKAGE
File Number
14
13
12
11
10
9
8
14
13
12
10
11
9
8
VCC
OE4
A4
Y4
OE3
A3
Y3
VCC
OE4
A4
Y4
OE3
A3
Y3
518817
3565.1