SST25WF512-40-5I-SAE SST [Silicon Storage Technology, Inc], SST25WF512-40-5I-SAE Datasheet
SST25WF512-40-5I-SAE
Related parts for SST25WF512-40-5I-SAE
SST25WF512-40-5I-SAE Summary of contents
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... SOIC (150 mils) – 8-contact WSON (5mm x 6mm) • All non-Pb (lead-free) devices are RoHS compliant single power supply of 1.65-1.95V for SST25WF512/010/ 020/040. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet Address Buffers and Latches CE# Note: In AAI mode, the SO pin functions as an RY/BY# pin when configured as a ready/busy status pin. See “End-of-Write Detection” on page 14 for more information. FIGURE 1: Functional Block Diagram ©2009 Silicon Storage Technology, Inc. ...
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... To reset the operation of the device and the internal logic. The device powers on with RST# pin functionality as default. To temporarily stop serial communication with SPI Flash memory while device is selected. This is selected by an instruction sequence which is detailed in “Reset/Hold Mode” on page 5. To provide power supply voltage: 1.65-1.95V for SST25WF512/010/020/040 3 Data Sheet CE ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet MEMORY ORGANIZATION The SST25WF512/010/020/040 SuperFlash memory arrays are organized in uniform 4 KByte with 16 KByte, 32 KByte, and 64 KByte (2 Mbit and 4 Mbit Only) overlay eras- able blocks. DEVICE OPERATION The SST25WF512/010/020/040 are accessed through the SPI (Serial Peripheral Interface) bus compatible proto- col. The SPI bus consist of four control lines ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Reset/Hold Mode The RST#/HOLD# pin provides either a hardware reset or a hold pin. From power-on, the RST#/HOLD# pin defaults as a hardware reset pin (RST#). The Hold mode for this pin is a user selected option where an Enable-Hold instruction enables the Hold mode ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet Hold The Hold operation enables the hold pin functionality of the RST#/HOLD# pin. Once set to hold pin mode, the RST#/ HOLD# pin continues functioning as a hold pin until the device is powered off and then powered on. After a power- off and power-on, the pin functionality returns to a reset pin (RST#) mode. See “ ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Status Register The software status register provides status on whether the flash memory array is available for any Read or Write oper- ation, whether the device is Write enabled, and the state of the Memory Write protection. During an internal Erase or ...
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... Block-Protect-Lock (BPL) bit is ‘0’. Chip-Erase can only be executed if Block-Protection bits are all ‘0’. After power- up, BP2, BP1, and BP0 are set to defaults. See Table 4 for defaults at power-up. TABLE 5: Software Status Register Block Protection for SST25WF512 Protection Level None 1 (Upper Quarter Memory) ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 TABLE 8: Software Status Register Block Protection for SST25WF040 Protection Level Protected Blocks None None 1 (Upper Eighth Memory) Blocks 14 through 15 2 (Upper Quarter Memory) Blocks 12 through 15 3 (Upper Half Memory) ...
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... Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instruc- tions. The complete instructions are provided in Tables 9 and 10. All instructions are synchronized off a high-to-low transition of CE#. Inputs will be accepted on the rising edge TABLE 9: Device Operation Instructions for SST25WF512 and SST25WF010 Instruction Description Read Read Memory ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 TABLE 10: Device Operation Instructions for SST25WF020 AND SST25WF040 Instruction Description Read Read Memory High-Speed Read Read Memory at Higher Speed 0000 1011b (0BH) 4 KByte Sector- Erase 4 KByte of memory 3 Erase array ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet Read (20 MHz) The Read instruction, 03H, supports MHz Read. The device outputs a data stream starting from the speci- fied address location. The data stream is continuous through all addresses until terminated by a low-to-high tran- sition on CE# ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet Auto Address Increment (AAI) Word-Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total program- ming time when multiple bytes or the entire memory array programmed ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 CE SCK REN Load AAI command, Address, 2 bytes data SO Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet Sector-Erase The Sector-Erase instruction clears all bits in the selected 4 KByte sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of any command sequence ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 64-KByte Block-Erase for SST25WF020 and SST25WF040 The Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area is ignored. Prior to any Write oper- ation, the Write-Enable (WREN) instruction must be exe- cuted ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction, 05H, allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Write-Disable (WRDI) The Write-Disable (WRDI) instruction, 04H, resets the Write-Enable-Latch bit and AAI to 0 disabling any new Write operations from occurring. The WRDI instruction will not terminate any programming operation in progress. Any ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet Enable-Hold (EHLD) The 8-bit command, AAH, Enable-Hold instruction enables the HOLD functionality of the RST#/HOLD# pin. CE# must remain active low for the duration of the Enable-Hold FIGURE 21: Enable-Hold Sequence Read-ID The Read-ID instruction identifies the manufacturer as SST and the device as SST25WF512/010/020/040 ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25WF512/010/020/040 and the manufacturer as SST. The device information can be read from executing the 8- bit command, 9FH. Following the JEDEC Read-ID instruc- tion, the 8-bit manufacturer’ ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Power-Up Specifications All functionalities and DC specifications are specified for less than 180 ms). If the VDD ramp rate is slower than 1V/100 µs, a hardware reset is required. The recom- mended V power-up to RESET# high time should be greater than 100 µs to ensure a proper reset. See Table 13 DD and Figures 24 and 25 for more information ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet Max DD Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. V Min DD FIGURE 25: Power-up Timing Diagram ©2009 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash T PU-READ T Device fully accessible ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 DC Characteristics TABLE 14: DC Operating Characteristics Symbol Parameter I Read Current DDR I Read Current DDR2 I Program and Erase Current DDW I Standby Current SB I Input Leakage Current LI I Output Leakage Current LO V Input Low Voltage ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet AC Characteristics TABLE 17: AC Operating Characteristics Symbol Parameter 1 F Serial Clock Frequency CLK T Serial Clock High Time SCKH T Serial Clock Low Time SCKL T Serial Clock Rise Time SCKR T Serial Clock Fall Time SCKF 2 T CE# Active Setup Time ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 CE# T CES T CHH SCK T DS MSB SI HIGH-Z SO FIGURE 26: Serial Input Timing Diagram CE# T SCKH SCK T CLZ SO SI FIGURE 27: Serial Output Timing Diagram ©2009 Silicon Storage Technology, Inc SCKR ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet CE# SCK SO SI HOLD# FIGURE 28: Hold Timing Diagram V IHT INPUT V ILT AC test inputs are driven at V (0.9V IHT inputs and outputs are V (0. FIGURE 29: AC Input/Output Reference Waveforms ©2009 Silicon Storage Technology, Inc. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 PRODUCT ORDERING INFORMATION SST 25 WF XXX - XXX - XX Valid combinations for SST25WF512 SST25WF512-40-5I-SAF Valid combinations for SST25WF010 SST25WF010-40-5I-SAF Valid combinations for SST25WF020 SST25WF020-40-5I-SAF SST25WF020-40-5I-QAE Valid combinations for SST25WF040 ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet PACKAGING DIAGRAMS Pin #1 Identifier TOP VIEW 5.0 4.8 4.00 3.80 6.20 5.80 Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads. ...
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... Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 TOP VIEW Pin #1 Corner 6.00 ± 0.10 Note: 1. All linear dimensions are in millimeters (max/min). 2. Untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. The external paddle is electrically connected to the die back-side and possibly to certain V This paddle can be soldered to the PC board ...
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... SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040 Data Sheet TABLE 18: Revision History Number 00 • Initial release of data sheet 01 • Removed “Commercial” Temperature Range • Added references to Tables 6 and 7 in “Block-Protection (BP2, BP1, BP0)” on page 8 • Modified EWSR and WREN footnote information and updated EBSY Op Code Cycle in Tables 9 and 10 • ...