SST25WF512-40-5I-SAE SST [Silicon Storage Technology, Inc], SST25WF512-40-5I-SAE Datasheet - Page 10

• Manufacturer Part Number: SST25WF512-40-5I-SAE
• Description: 512 Kbit / 1 Mbit / 2 Mbit / 4Mbit 1.8V SPI Serial Flash
• Manufacturer: SST [Silicon Storage Technology, Inc]

Data Sheet
INSTRUCTIONS
Instructions are used to read, write (Erase and Program),
and configure the SST25WF512/010/020/040. The
instruction bus cycles are 8 bits each for commands (Op
Code), data, and addresses. The Write-Enable (WREN)
instruction must be executed prior to Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, Write-Status-Register, or Chip-Erase instruc-
tions. The complete instructions are provided in Tables 9
and 10. All instructions are synchronized off a high-to-low
transition of CE#. Inputs will be accepted on the rising edge
TABLE 9: Device Operation Instructions for SST25WF512 and SST25WF010
©2009 Silicon Storage Technology, Inc.
Instruction
Read
High-Speed Read
4 KByte Sector-
Erase
32 KByte Block-
Erase
Chip-Erase
Byte-Program
AAI-Word-Program
RDSR
EWSR
WRSR
WREN
WRDI
RDID
EBSY
DBSY
JEDEC-ID
EHLD
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be V
3. 4 KByte Sector-Erase addresses: use A
4. 32 KByte Block-Erase addresses: use A
5. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
7. Either EWSR or WREN followed by WRSR will write to the Status register. The EWSR-WRSR sequence provides backward compat-
8. Manufacturer’s ID is read with A
programmed. Data Byte 0 will be programmed into the initial address [A
initial address [A
ibility to the SST25VF/LF series. The WREN-WRSR sequence is recommended for new designs.
device ID output stream is continuous until terminated by a low-to-high transition on CE#.
8
3
4
6
7
7
5
23
-A
Description
Read Memory at Higher Speed 0000 1011b (0BH)
Erase Full Memory Array
To Program One Data Byte
Write-Status-Register
Write-Disable
Enable SO to output RY/BY#
JEDEC ID read
Read Memory
Erase 4 KByte of
memory array
Erase 32 KByte block
of memory array
Auto Address Increment
Programming
Read-Status-Register
Enable-Write-Status-Register
Write-Enable
Read-ID
status during AAI programming
Disable SO to output RY/BY#
status during AAI programming
Enable HOLD# pin functionality
of the RST#/HOLD# pin
1
] with A
0
= 1.
0
=0, and Device ID is read with A
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
MS
MS
-A
-A
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
12,
15,
remaining addresses are don’t care but must be set either at V
remaining addresses are don’t care but must be set either at V
0000 0011b (03H)
0000 0010b (02H)
0000 0101b (05H)
0110 0000b (50H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 1111b (9FH)
Op Code Cycle
0010 0000b (20H)
0101 0010b (52H)
0110 0000b (60H) or
1100 0111b (C7H)
1010 1101b (ADH)
1001 0000b (90H) or
1010 1011b (ABH)
0111 0000b (70H)
1000 0000b (80H)
1010 1010b (AAH)
10
0
=1. All other address bits are 00H. The Manufacturer’s ID and
IL
of SCK starting with the most significant bit. CE# must be
driven low before an instruction is entered and must be
driven high after the last bit of the instruction has been
shifted in (except for Read, Read-ID, and Read-Status-
Register instructions). Any low-to-high transition on CE#,
before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device
to standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most significant
bit (MSB) first.
or V
23
-A
IH
1
.
1
] with A
Cycle(s)
0
Address
=0, Data Byte 1 will be programmed into the
3
3
3
3
0
3
3
0
0
0
0
0
3
0
0
0
0
2
Cycle(s)
Dummy
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Cycle(s)
IL
IL
1 to ∞
1 to ∞
2 to ∞
1 to ∞
1 to ∞
3 to ∞
Data
or V
or V
0
0
0
1
0
1
0
0
0
0
0
S71328-08-000
IH.
IH.
Frequency
Maximum
20 MHz
40 MHz
T9.0 1328
11/09