em78f644nso28s ELAN Microelectronics Corp, em78f644nso28s Datasheet - Page 84

• Manufacturer Part Number: em78f644nso28s
• Description: Flash Series 8-bit Microcontroller
• Manufacturer: ELAN Microelectronics Corp

EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
74 •
In Timer mode, counting up is performed using internal clock. When the contents of
up-counter match the TCR1DA, the interrupt is then generated and the counter is
cleared. Counting up resumes after the counter is cleared. The current contents of
up-counter are loaded into TCR1DB by setting TC1CAP to “1” and the TC1CAP is
cleared to “0” after capture is completed automatically.
In Counter mode, counting up is performed using external clock input pin (TC1 pin)
and either rising or falling edge can be selected by TC1ES, but both edges can not
be used. When the contents of up-counter match the TCR1DA, the interrupt is then
generated and the counter is cleared. Counting up resumes after the counter is
cleared. The current contents of up-counter are loaded into TCR1DB by setting
TC1CAP to “1” and the TC1CAP is cleared to “0” after capture is completed
automatically.
In Capture mode, the pulse width, period, and duty of the TC1 input pin are measured
under this mode to decode the remote control signal. The counter is made free
running by the internal clock. On the rising (falling) edge of TC1 pin input, the
contents of counter are loaded into TCR1DA, then the counter is cleared and the
interrupt is generated. On the falling (rising) edge of TC1 pin input, the contents of
counter are loaded into TCR1DB. At the next rising edge of TC1 pin input while the
counter is still counting, the contents of counter are loaded into TCR1DA. Then the
counter is cleared and the interrupt is generated again. If an overflow is detected
before the edge, the FFH is loaded into TCR1DA and the overflow interrupt is
generated. During the interrupt process, you can check and determine an overflow
has occurred by checking the TCR1DA value is FFH. After an interrupt (capture to
TCR1DA or overflow detected) is generated, capture and overflow detection are
halted until TCR1DA is read out.
Figure 6-8b Capture Mode Timing Diagram
(This specification is subject to change without further notice)
Product Specification (V1.0) 05.05.2010