ax88796blf ASIX Electronics Corporation, ax88796blf Datasheet - Page 28

• Manufacturer Part Number: ax88796blf
• Description: Low-pin-count Non-pci 8/16-bit 10/100m Fast Ethernet Controller
• Manufacturer: ASIX Electronics Corporation

4.7 EEPROM Interface
4.8 Power management
AX88796B can optionally load its MAC address from an external serial EEPROM. If a properly configured
EEPROM is detected by AX88796B at power-up, hard reset or host set a reload EEPROM request (CR page3 offset
0Ch), the constants of EEPROM data will be auto loading to internal memory from 0000h to 001Fh and from 0400h
to 040Fh automatically. It is similar NE2000 PROM store MAC address field. A detailed explanation of the
EEPROM data format in section 3.1 “EEPROM Memory Mapping”. After auto load EEPROM completed not
indicate AX88796B knew its MAC address. Host driver can get MAC address from internal memory (0000h ~
001Fh) or (0400h ~ 040Fh) and write “Physical Address Registers” (CR page1 offset 01h ~ 06h).
The AX88796B EEPROM use 3 PIN to connect to a most “93C46” type EEPROM configured for x16-bit operation.
A connect diagram as below
After EEPROM loader has finished reading the MAC after power-on, hard reset or host set a reload EEPROM
request (CR page3 offset 0Ch), the Host is free to perform EECS, EECK and EEDIO as General Purpose I/O pin.
AX88796B supports power-down modes to allow applications to minimize power consumption. There is one
normal operation power state, D0 and there are two power saving states: D1, and D2. The “Power Management
Register”(CR Page3 Offset 0Bh) controls those of power management modes. In D1 power saving state, AX88796B
supports Wake on LAN function. In D2 power saving state, AX88796B will off all function block and clocks to
minimize power consumption. After wakeup event, the “Power Management Register” will be cleared and state at
normal operation power state. When AX88796B in either D1 or D2 power saving mode, host can write “Host Wake
Up Register” (Offset 1Fh) return the AX88796B to the D0 state. Power is reduced to various modules by disabling
the clocks as outlined in table as below.
management
MAC power
AX88796B
MAC and
BLOCK
Internal
AX88796B
clock
PHY
Host
EEDIO
EECK
EECS
Tab - 12 Power Management Statuses
operation)
Fig - 7 EEPROM connections
(Normal
D0
On
On
On
On
Rx Block
28
(WOL)
Off
D1
On
On
On
EECS
EECK
EEDI
EEDO
93C46
AX88796BLF / AX88796BLI
Off
Off
Off
Off
D2
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