ax88796blf ASIX Electronics Corporation, ax88796blf Datasheet - Page 46

• Manufacturer Part Number: ax88796blf
• Description: Low-pin-count Non-pci 8/16-bit 10/100m Fast Ethernet Controller
• Manufacturer: ASIX Electronics Corporation

5.1.52 Wakeup Frame Offset (WFOFST)
Page3 Offset 07H (Read/Write)
5.1.53 Wakeup Frame Last Byte (WFLB)
Page3 Offset 08H (Read/Write)
5.1.54 Wakeup Frame Command (WFCMD)
Page3 Offset 09H (Read/Write)
5.1.55 Wakeup Control and Status Register (WUCSR)
Page3 Offset 0AH (Read/Write)
Field
7:0
15:8
23:16
31:24
Field
7:0
15:8
23:16
31:24
Field
3:0
7:4
11:8
15:12
19:16
31:18
Field
7
6
5
4
3
2
1
WF1OFST Byte mask Offset for wake-up frame filter 1.
WF2OFST Byte mask Offset for wake-up frame filter 2.
WF3OFST Byte mask Offset for wake-up frame filter 3.
-
-
WUFR
MPR
-
LSCWE
Name
WF0OFST Byte mask Offset for wake-up frame filter 0. Host continue write 4 times to completed
Name
WFLB0
WFLB1
WFLB2
WFLB3
Name
WFCMD0 Byte Mask Command for wake-up frame filter 0. Host continue write 4 times to completed
WFCMD1 Byte Mask Command for wake-up frame filter 1.
WFCMD2 Byte Mask Command for wake-up frame filter 2.
WFCMD3 Byte Mask Command for wake-up frame filter 3.
WFCSCD
Name
LSC
WUEN
Reserved. Always zero.
Description (Default = 00h)
32-bits of Byte Mask 3, 2, 1, 0 Offset. The unit is 16-bit. (2bytes)
Description (Default = 00h)
Mask Last Byte for wake-up frame filter 0. Host continue write 4 times to completed
32-bits of Last Byte of 3, 2, 1, 0 filter.
Mask Last Byte for wake-up frame filter 1.
Mask Last Byte for wake-up frame filter 2.
Mask Last Byte for wake-up frame filter 3.
Description (Default = 00h)
32-bits of Byte Mask Command of 3, 2, 1, 0 filter and Mask cascade commend.
Bit0: wake-up frame filter enable
Bit1: destination match enable
Bit2: Multicast match enable
Bit3: Reserved
Byte Mask Cascade Command for wake-up frame filter
Bit-0: cascade wake-up filter 1 and 0
Bit-1: cascade wake-up filter 2 and 1
Bit-2: cascade wake-up filter 3 and 2
Description (Default = 00h)
Reserved
Link status change event flag. This bit will be clear when Host write PMR or set this bit.
Wake-up Frame Received event flag. This bit will be clear when Host write PMR or set
this bit.
Magic Packet Received event flag. This bit will be clear when Host write PMR or set this
bit.
Reserved
Link status change wakeup enable
0: disable (Default)
1: enable
Wake-up frame enable
0: disable (Default)
1: enable
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AX88796BLF / AX88796BLI
ASIX ELECTRONICS CORPORATION