LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 139

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

MSG
C/D
I/O
This register returns the SCSI control line status. A bit is set when the
corresponding SCSI control line is asserted. These bits are not latched;
they are a true representation of what is on the SCSI bus at the time the
register is read. The resulting read data is synchronized before being
presented to the PCI bus to prevent parity errors from being passed to
the system. This register is used for diagnostics testing or operation in
low level mode.
Register: 0x0C (0x8C)
DMA Status (DSTAT)
Read Only
Reading this register clears any bits that are set at the time the register
is read, but does not necessarily clear the register because additional
interrupts are pending (the LSI53C875 stacks interrupts). The DIP bit in
the
DMA interrupt conditions individually through the
(DIEN)
When performing consecutive 8-bit reads of the
SCSI Interrupt Status Zero
(SIST1)
periods between the reads to ensure that the interrupts clear properly.
See
interrupts.
DFE
DFE
Interrupt Status (ISTAT)
7
1
Chapter 2, “Functional Description,”
register.
registers (in any order), insert a delay equivalent to 12 CLK
MDPE
6
0
SMSG/ Status
SC_D/ Status
SI_O/ Status
DMA FIFO Empty
This status bit is set when the DMA FIFO is empty. It is
possible to use it to determine if any data resides in the
FIFO when an error occurs and an interrupt is generated.
This bit is a pure status bit and does not cause an
interrupt.
BF
5
0
register is also cleared. It is possible to mask
(SIST0), and
ABRT
4
0
SSI
3
0
for more information on
SCSI Interrupt Status One
SIR
DMA Status
2
0
DMA Interrupt Enable
R
1
x
(DSTAT),
IID
0
0
5-23
2
1
0
7