LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 32

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.5 PCI Cache Mode
2.5.1 Load/Store Instructions
2-8
necessary since there are internal pull-ups on the MAD bus. The internal
pull-up resistors are disabled when external pull-down resistors are
detected, to reduce current drain.
The LSI53C875 allows the system to determine the size of the available
external memory using the
PCI configuration space. For more information on how this works, refer
to the PCI specification or the
description in
MAD[0] is the slow ROM pin. When pulled down, it enables two extra
clock cycles of data access time to allow use of slower memory devices.
The external memory interface also supports updates to Flash memory.
The 12 V power supply for Flash memory, V
with the GPIO4 pin and the GPIO4 control bit. For more information on
the GPIO4 pin, refer to
The LSI53C875 supports the PCI specification for an 8-bit
Size
register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the
Line Size
Write and Invalidate are each software enabled or disabled to allow the
user full flexibility in using these commands. For more information on PCI
cache mode operations, refer to
The LSI53C875 supports the Load and Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the chip to transfer bytes to addresses relative
to the
the Load and Store instructions, refer to
I/O Processor.”
Functional Description
register located in PCI configuration space. The
Data Structure Address (DSA)
register, the PCI commands Read Line, Read Multiple, and
Chapter 3, “PCI Functional Description.”
Chapter 4, “Signal Descriptions.”
Expansion ROM Base Address
Expansion ROM Base Address
Chapter 3, “PCI Functional Description.”
register. For more information on
Chapter 6, “Instruction Set of the
PP
, is enabled and disabled
Cache Line Size
Cache Line
register in
register
Cache