LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 26

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.1.2 DMA Core
2.1.3 SCRIPTS Processor
2-2
The SCSI core offers low level register access or a high level control
interface. Like first generation SCSI devices, the LSI53C875 SCSI core
can be accessed as a register oriented device. The ability to sample
and/or assert any signal on the SCSI bus can be used in error recovery
and diagnostic procedures. In support of loopback diagnostics, the SCSI
core may perform a self-selection and operate as both an initiator and a
target.
The LSI53C875 SCSI core is controlled by the integrated SCRIPTS
processor through a high level logical interface. Commands controlling
the SCSI core are fetched out of the main host memory or local memory.
These commands instruct the SCSI core to Select, Reselect, Disconnect,
Wait for a Disconnect, Transfer Information, Change Bus Phases and, in
general, implement all aspects of the SCSI protocol. The SCRIPTS
processor is a special high speed processor optimized for SCSI protocol.
The DMA core is a bus master DMA device that attaches directly to the
industry standard PCI Bus. The DMA core is tightly coupled to the SCSI
core through the SCRIPTS processor, which supports uninterrupted
scatter/gather memory operations.
The LSI53C875 supports 32-bit memory and automatically supports
misaligned DMA transfers. A 536-byte FIFO allows the LSI53C875 to
support 2, 4, 8, 16, 32, 64, or 128 longword bursts across the PCI bus
interface.
The SCSI SCRIPTS processor allows both DMA and SCSI commands
to be fetched from host memory or internal SCRIPTS RAM. Algorithms
written in SCSI SCRIPTS control the actions of the SCSI and DMA cores
and are executed from 32-bit system RAM. The SCRIPTS processor
executes complex SCSI bus sequences independently of the host CPU.
The SCRIPTS processor can begin a SCSI I/O operation in
approximately 500 ns. This compares with 2–8 ms required for traditional
intelligent host adapters. Algorithms may be designed to tune SCSI bus
performance, to adjust to new bus device types (such as scanners,
communication gateways, etc.), or to incorporate changes in the SCSI-2
Functional Description