LSI53C875 LSI Logic, LSI53C875 Datasheet - Page 59

• Manufacturer Part Number: LSI53C875
• Description: PCI to Ultra SCSI I/O Processor
• Manufacturer: LSI Logic

2.5.14.1 Wide SCSI Send Bit
Figure 2.6
CHMOV 5, 3 when Data_Out
Moves five bytes from address 0x03 in the host memory to the SCSI bus.
Bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in
the low-order byte of the
is combined with the first byte of the following MOVE instruction.
Move 5, 9 when Data_Out
Moves five bytes from address 0x09 in the host memory to the SCSI bus.
The WSS bit is set whenever the SCSI controller is sending data
(Data-Out for initiator or Data-In for target) and the controller detects a
partial transfer at the end of a chained Block Move SCRIPTS instruction
(this flag is not set if a normal Block Move instruction is used). Under this
condition, the SCSI controller does not send the low-order byte of the last
partial memory transfer across the SCSI bus. Instead, the low-order byte
is temporarily stored in the lower byte of the
(SODL)
flag to determine what behavior must occur at the start of the next data
PCI Cache Mode
0x0B 0x0A 0x09 0x08
0x0F 0x0E 0x0D 0x0C
0x03 0x02 0x01 0x00
0x07 0x06 0x05 0x04
0x13 0x12 0x11 0x10
Host Memory
register and the WSS flag is set. The hardware uses the WSS
32 Bits
Block Move and Chained Block Move Instructions
SCSI Output Data Latch (SODL)
00
04
08
0C
10
0x0B 0x0A
0x0D 0x0C
0x04 0x03
0x06 0x05
0x09 0x07
SCSI Bus
16 Bits
SCSI Output Data Latch
register and
2-35