AD8400AN10 Analog Devices, AD8400AN10 Datasheet - Page 13

• Manufacturer Part Number: AD8400AN10
• Description: 1-/2-/4-Channel Digital Potentiometers
• Manufacturer: Analog Devices

where Dx is the data contained in the 8-bit RDAC# latch, and
R
V
resistance values will be set for the following RDAC latch codes
(applies to 10 k potentiometers):
D
(Dec)
255
128
1
0
The typical distribution of R
within 1%. However, device-to-device matching is process lot
dependent having a 20% variation. The change in R
temperature has a positive 500 ppm/ C temperature coefficient.
The wiper-to-end-terminal resistance temperature coefficient
has the best performance over the 10% to 100% of adjustment
range where the internal wiper contact switches do not contribute
any significant temperature related errors. The graph in Figure
11 shows the performance of R
trimmer with codes below 32 results in the larger temperature
coefficients plotted.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting A terminal to +5 V and B terminal to
ground produces an output voltage at the wiper starting at zero
volts up to 1 LSB less than +5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256
position resolution of the potentiometer divider. The general
equation defining the output voltage with respect to ground for
any given input voltage applied to terminals AB is:
Operation of the digital potentiometer in the divider mode re-
sults in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors,
not the absolute value; therefore, the temperature drift improves
to 15 ppm/ C.
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases due to the contributions of the
CMOS switch wiper resistance becoming an appreciable portion
of the total resistance from terminal B to the wiper. See Figure 10
for a plot of potentiometer tempco performance versus code
setting.
DIGITAL INTERFACING
The AD8400/AD8402/AD8403 contains a standard SPI com-
patible three-wire serial input control interface. The three inputs
are clock (CLK), CS and serial data input (SDI). The positive-
edge sensitive CLK input requires clean transitions to avoid
clocking incorrect data into the serial input register. For best re-
sults use logic transitions faster than 1 V/ s. Standard logic
families work well. If mechanical switches are used for product
evaluation, they should be debounced by a flip-flop or other
REV. B
BA
A
= 0 V and B terminal is open circuit, the following output
is the nominal end-to-end resistance. For example, when
V
W
(Dx) = Dx/256
R
( )
89
5050
10011
10050
WA
BA
Full Scale
Midscale (RS = 0 Condition)
1 LSB
Zero Scale
Output State
from channel-to-channel matches
V
WB
AB
tempco vs. code, using the
+ V
B
Equation 4
BA
with
–13–
suitable means. The Figure 38 block diagrams show more detail
of the internal digital circuitry. When CS is taken active low, the
clock loads data into the 10-bit serial register on each positive
clock edge (see Table II).
SHDN
SDO
CLK
SDI
CS
SHDN
CLK
SDI
CLK
CS
SDI
CS
DGND
DO
DI
REG
SER
DI
DGND
10-BIT
DI
Figure 38. Block Diagrams
SER
REG
10-BIT
A1
A0
D7
D0
SER
REG
A1
A0
D7
D0
A1
A0
D0
D7
AD8400/AD8402/AD8403
8
8
ADDR
8
DEC
EN
ADDR
DEC
EN
ADDR
DEC
EN
RS
RS
a.
b.
c.
D7
D0
D7
D0
D7
D0
D7
D0
D7
D0
DAC
LAT
#1
DAC
LAT
DAC
LAT
R
#1
#2
R
R
DAC
DAC
R
R
LAT
LAT
AD8400
#1
#4
R
R
R
R
AD8403
AD8402
GND
AGND
AGND
V
A1
W1
B1
V
A1
W1
B1
A4
W4
B4
DD
DD
A4
B4
V
A1
W1
B1
W4
DD