AD8400AN10 Analog Devices, AD8400AN10 Datasheet - Page 14

• Manufacturer Part Number: AD8400AN10
• Description: 1-/2-/4-Channel Digital Potentiometers
• Manufacturer: Analog Devices

AD8400/AD8402/AD8403
CLK CS
L
P
X
X
X
X
X
NOTE: P = positive edge, X = don’t care, SR = shift register.
The serial data-output (SDO) pin contains an open drain n-
channel FET. This output requires a pull-up resistor in order to
transfer data to the next package’s SDI pin. The pull-up resistor
termination voltage may be larger than the V
than max V
e.g., the AD8403 could operate at V
for interface to the next device could be set at +5 V. This allows
for daisy chaining several RDACs from a single processor serial
data line. The clock period needs to be increased when using a
pull-up resistor to the SDI pin of the following device in the
series. Capacitive loading at the daisy chain node SDO–SDI
between devices must be accounted for to successfully transfer
data. When daisy chaining is used, the CS should be kept low
until all the bits of every package are clocked into their respec-
tive serial registers insuring that the address bits and data bits
are in the proper decoding location. This would require 20 bits
of address and data complying to the word format provided in
Table I if two AD8403 four-channel RDACs are daisy chained.
Note, only the AD8403 has a SDO pin. During shutdown
SHDN the SDO output pin is forced to the off (logic high state)
to disable power dissipation in the pull up resistor. See Figure 40
for equivalent SDO output circuit schematic.
The data setup and data hold times in the specification table de-
termine the data valid time requirements. The last 10 bits of the
data word entered into the serial register are held when CS re-
turns high. At the same time CS goes high it gates the address
decoder, which enables one of the two (AD8402) or four
(AD8403) positive edge triggered RDAC latches. See Figure 39
detail and Table III Address Decode Table.
A1
0
0
1
1
L
L
P
H
X
H
H
Table II. Input Logic Control Truth Table
DD
RS
H
H
H
H
L
P
H
of +8 V) of the AD8403 SDO output device,
Table III. Address Decode Table
A0
0
1
0
1
SHDN Register Activity
H
H
H
H
H
H
L
No SR effect, enables SDO pin.
Shift One bit in from the SDI pin.
The tenth previously entered bit is
shifted out of the SDO pin.
Load SR data into RDAC latch
based on A1, A0 decode (Table III).
No Operation.
Sets all RDAC latches to midscale,
wiper centered, and SDO latch
cleared.
Latches all RDAC latches to 80
Open circuits all resistor
A–terminals, connects W to B,
turns off SDO output transistor.
DD
Latch Decoded
RDAC#1
RDAC#2
RDAC#3 AD8403 Only
RDAC#4 AD8403 Only
= 3.3 V and the pull-up
DD
supply (but less
H
.
–14–
The target RDAC latch is loaded with the last eight bits of the
serial data word completing one DAC update. In the case of the
AD8403 four separate 10-bit data words must be clocked in to
change all four VR settings.
All digital pins are protected with a series input resistor and par-
allel Zener ESD structure shown in Figure 41a. This structure
applies to digital pins CS, SDI, SDO, RS, SHDN, CLK. The
digital input ESD protection allows for mixed power supply
applications where +5 V CMOS logic can be used to drive an
AD8400/AD8402 or AD8403 operating from a +3 V power sup-
ply. The analog pins A, B, W are protected with a 20
resistor and parallel Zener, see Figure 41b.
C
Figure 40. Detail SDO Output Schematic of the AD8403
Figure 41b. Equivalent ESD Protection Circuit (Analog
Pins)
Figure 42. RDAC Circuit Simulation Model for RDAC =
10 k
A
= 90.4pF · (
Figure 41a. Equivalent ESD Protection Circuits
Figure 39. Equivalent Input Control Logic
SHDN
CLK
256
SDI
DW
CS
RS
CLK
SDI
CS
) + 30pF
A
REGISTER
DIGITAL
C
SERIAL
A
PINS
A, B, W
AD8403
RDAC
10k
D
CK RS
W
1k
20
120pF
Q
C
DECODE
W
REGISTER
ADDR
SERIAL
C
LOGIC
B
C
B
RDAC 1
RDAC 2
RDAC 4
B
= 90.4pF · (1 –
SDO
DW
256
series
REV. B
) + 30pF