AD8400AN10 Analog Devices, AD8400AN10 Datasheet - Page 15

• Manufacturer Part Number: AD8400AN10
• Description: 1-/2-/4-Channel Digital Potentiometers
• Manufacturer: Analog Devices

The ac characteristics of the RDACs are dominated by the inter-
nal parasitic capacitances and the external capacitive loads. The
–3 dB bandwidth of the AD8403AN10 (10 k resistor) mea-
sures 600 kHz at half scale as a potentiometer divider. Figure 23
provides the large signal BODE plot characteristics of the three
available resistor versions 10 k , 50 k , and 100 k . The gain
flatness versus frequency graph, Figure 26, predicts filter appli-
cations performance. A parasitic simulation model has been de-
veloped, and is shown in Figure 42. Listing I provides a macro
model net list for the 10 k RDAC:
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,)
*
CA
RAW
CW
RBW
CB
*
.ENDS DPOT
The total harmonic distortion plus noise (THD+N) is measured
at 0.003% in an inverting op amp circuit using an offset ground
and a rail-to-rail OP279 amplifier, Figure 33. Thermal noise is
primarily Johnson noise, typically 9 nV/ Hz for the 10 k ver-
sion at f = 1 kHz. For the 100 k device, thermal noise becomes
29 nV/ Hz. Channel-to-channel crosstalk measures less than
–65 dB at f = 100 kHz. To achieve this isolation, the extra ground
pins provided on the package to segregate the individual RDACs
must be connected to circuit ground. AGND and DGND pins
should be at the same voltage potential. Any unused potentio-
meters in a package should be connected to ground. Power sup-
ply rejection is typically –35 dB at 10 kHz (care is needed to
minimize power supply ripple in high accuracy applications).
APPLICATIONS
The digital potentiometer (RDAC) allows many of the applica-
tions of trimming potentiometers to be replaced by a solid-state
solution offering compact size, freedom from vibration, shock
and open contact problems encountered in hostile environ-
ments. A major advantage of the digital potentiometer is its
programmability. Any settings can be saved for later recall in
system memory.
The two major configurations of the RDAC include the
potentiometer divider (basic 3-terminal application) and the
rheostat (2-terminal configuration) connections shown in
Figures 29 and 30.
REV. B
A 0 {DW/256*90.4E-12+30E-12}
A W {(1-DW/256)*RDAC+50}
W 0 120E-12
W B {DW/256*RDAC+50}
B 0 {(1-DW/256)*90.4E-12+30E-12}
Listing I. Macro Model Net List for RDAC
–15–
Certain boundary conditions must be satisfied for proper
AD8400/AD8402/AD8403 operation. First, all analog signals
must remain within the 0 to V
single-supply AD8400/AD8402/AD8403 products. For standard
potentiometer divider applications, the wiper output can be
used directly. For low resistance loads, buffer the wiper with a
suitable rail-to-rail op amp such as the OP291 or the OP279.
Second, for ac signals and bipolar dc adjustment applications, a
virtual ground will generally be needed. Whatever method is
used to create the virtual ground, the result must provide the
necessary sink and source current for all connected loads, in-
cluding adequate bypass capacitance. Figure 33 shows one
channel of the AD8402 connected in an inverting program-
mable gain amplifier circuit. The virtual ground is set at +2.5 V
which allows the circuit output to span a 2.5 volt range with
respect to virtual ground. The rail-to-rail amplifier capability is
necessary for the widest output swing. As the wiper is adjusted
from its midscale reset position (80
(code FF
cessfully larger increments. Alternatively, as the wiper is ad-
justed toward the B terminal (code 00
attenuated. The plot in Figure 43 shows the wiper settings for a
100:1 range of voltage gain (V/V). Note the 10 dB of pseudo-
logarithmic gain around 0 dB (1 V/V). This circuit is mainly
useful for gain adjustments in the range of 0.14 V/V to 4 V/V;
beyond this range the step sizes become very large and the resis-
tance of the driving circuit can become a significant term in the
gain equation.
Figure 43. Inverting Programmable Gain Plot
256
224
192
160
128
H
96
64
32
0
), the voltage gain of the circuit is increased in suc-
0.1
AD8400/AD8402/AD8403
INVERTING GAIN – V/V
DD
range used to operate the
1.0
H
) toward the A terminal
H
), the signal becomes
10