AD8400AN10 Analog Devices, AD8400AN10 Datasheet - Page 2

• Manufacturer Part Number: AD8400AN10
• Description: 1-/2-/4-Channel Digital Potentiometers
• Manufacturer: Analog Devices

AD8400/AD8402/AD8403–SPECIFICATIONS
10 k VERSION
ELECTRICAL CHARACTERISTICS
Parameter
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs
RESISTOR TERMINALS
DIGITAL INPUTS & OUTPUTS
POWER SUPPLIES
DYNAMIC CHARACTERISTICS
NOTES FOR 10 k VERSION
10
11
Specifications subject to change without notice.
4
1
2
3
5
6
7
8
9
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit.
I
resistor terminals are left open circuit.
Typicals represent average readings at +25 C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
V
INL and DNL are measured at V
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I
P
All Dynamic Characteristics use V
Measured at a V
DNL Specification limits of 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit.
W
Resistor Differential NL
Resistor Nonlinearity
Nominal Resistance
Resistance Tempco
Wiper Resistance
Nominal Resistance Match
Resolution
Integral Nonlinearity
Differential Nonlinearity
Voltage Divider Tempco
Full-Scale Error
Zero-Scale Error
Voltage Range
Capacitance
Capacitance
Shutdown Current
Shutdown Wiper Resistance
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
Power Dissipation (CMOS)
Power Supply Sensitivity
Bandwidth –3 dB
Total Harmonic Distortion
V
Resistor Noise Voltage
Crosstalk
DISS
AB
= 50 A for V
W
= V
Settling Time
is calculated from (I
DD
, Wiper (V
11
6
6
DD
W
Ax, Bx
Wx
5
pin where an adjacent V
= +3 V and I
W
) = No Connect.
6
7
3
4
DD
2
8
2
4
V
DD
W
W
9
DD
= 400 A for V
). CMOS logic level inputs result in minimum power dissipation.
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
= +5 V.
6, 10
W
pin is making a full-scale voltage change.
Symbol
R-DNL
R-INL
R
R
N
INL
DNL
DNL
DNL
V
V
C
C
I
R
V
V
V
V
V
V
I
C
V
I
I
P
PSS
PSS
BW_10K
THD
t
e
C
V
DD
S
A_SD
IL
DD
DD
NWB
R
R/R
V
DISS
W
WFSE
WZSE
A, B, W
W_SD
IH
IL
IH
IL
OH
OL
DD
A, B
W
IL
T
DD
= +5 V for the 10 k versions.
AB
W
= +5 V.
/ T
Range
/ T
O
W
(V
otherwise noted)
DD
= +3 V
Conditions
R
R
T
V
I
CH 1 to 2, 3, or 4, V
V
V
V
Code = 80
Code = FF
Code = 00
f = 1 MHz, Measured to GND, Code = 80
f = 1 MHz, Measured to GND, Code = 80
V
V
V
V
V
V
R
I
V
V
V
V
V
V
R = 10 k
V
V
R
V
W
OL
AB
DD
DD
DD
A
A
DD
DD
DD
DD
IN
IH
IH
IH
DD
DD
A
A
A
WB
WB
A
L
WB
= 1 V/R
= 1 V rms + 2 V dc, V
= V
= V
= V
= 1 k to V
= V
= +25 C, Model: AD840XYY10
= 1.6 mA, V
, V
, V
= V
= 0 V or +5 V, V
= V
= 2.4 V or 0.8 V, V
= V
= +5 V
= +3 V
= +3 V
= +5 V
= +5 V
= +3 V
= +3 V
= +5 V
= +3 V
= 5 k , f = 1 kHz, RS = 0
DD
A
A
DD
DD
DD
DD
DD
DD
= NC
= NC
10% or + 5 V
, V
, V
, V
, V
, Wiper = No Connect
H
H
–2–
or V
or V
H
B
B
B
B
= 0 V
= 0 V, SHDN = 0, V
= 0 V, SHDN = 0
= 0 V, 1% Error Band
10%
10%
DD
IL
IL
DD
T
T
= 0 V
= 0 V, V
A
A
= +5 V
= +25 C
= –40 C, +85 C
AB
DD
= V
DD
= +5 V
B
10%, V
= 2 V dc, f = 1 kHz
DD
= +5.5 V
DD
= +5.5 V
, T
A
A
= +V
= +25 C
DD
= +5 V
DD
, V
H
H
B
= 0 V, –40 C T
Min
–1
–2
8
8
–2
–1
–1
–1.5
–4
0
0
2.4
2.1
V
2.7
DD
–0.1
A
Typ
10
500
50
0.2
15
–2.8
+1.3
75
120
0.01
100
5
0.01
0.9
0.0002 0.001
0.006
600
0.003
2
9
–65
= V
1/4
1/2
1/2
1/4
1/4
1/2
DD
A
1
DD
versus logic voltage.
+85 C unless
and V
Max
+1
+2
12
100
1
+2
+1
+1
+1.5
0
+2
V
5
200
0.8
0.6
0.4
5.5
5
4
27.5
0.03
1
DD
B
= 0 V.
REV. B
Units
LSB
LSB
k
ppm/ C
%
Bits
LSB
LSB
LSB
LSB
ppm/ C
LSB
LSB
V
pF
pF
V
V
V
V
V
V
pF
V
mA
%/%
%/%
kHz
%
nV/ Hz
dB
A
A
A
W
s