XC2S400E6Fxxx Xilinx, XC2S400E6Fxxx Datasheet
XC2S400E6Fxxx
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XC2S400E6Fxxx Summary of contents
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... Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...
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... User I/O counts include the four global clock/user input pins. See details in © 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...
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... FPGA. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes. Xilinx offers multiple types of low-cost configuration solutions including the Platform Flash in-system programmable configuration PROMs. ...
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... Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information Available User I/O According to Package Type TQ144 PQ208 TQG144 PQG208 102 146 102 146 - 146 - 146 - 146 - - - - www.xilinx.com 1-800-255-7778 FT256 FG456 FTG256 FGG456 FGG676 182 - 182 202 182 265 182 289 182 329 182 329 - ...
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... FG(G)456 456-ball Fine Pitch BGA FG(G)676 676-ball Fine Pitch BGA R SPARTAN R XC2S50E PQ208xxx0425 Package xxxxxxxxx Speed 6C Sample package with part marking for XC2S50E-6PQ208C. www.xilinx.com 1-800-255-7778 Temperature Range Number of Pins DS077-1_03a_072004 Temperature Range Number of Pins Pb-free DS077-1_03b_072004 Temperature Range ( Commercial 0°C to +85° Industrial – ...
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... Added information on Pb-free packaging options. DS077-1 (v2.2) July 28, 2004 Product Specification Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information Functional Description (Module 2) DC and Switching Characteristics Pinout Tables (Module 4) Description Table 2 to show that all products are available. Clarified www.xilinx.com 1-800-255-7778 (Module 3) 5 ...
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... Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information 6 www.xilinx.com 1-800-255-7778 R DS077-1 (v2.2) July 28, 2004 Product Specification ...
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... Figure 1: Basic Spartan-IIE Family FPGA Block Diagram © 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...
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... N/A All pads are protected against damage from electrostatic 2.5 N/A discharge (ESD) and from over-voltage transients. After 3.3 N/A configuration, clamping diodes are connected to V LVTTL, PCI, HSTL, SSTL, CTT, and AGP standards. www.xilinx.com 1-800-255-7778 R for CCO DS077-2 (v2.1) July 9, 2003 Product Specification ...
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... REF 1.5V Some input standards require a user-supplied threshold voltage, V matically configured as inputs for the V CCO one in six of the I/O pins in the bank assume this role. www.xilinx.com 1-800-255-7778 Figure 3). The pinout tables Pinout pins which must CCO Bank 0 Bank 1 GCLK3 GCLK2 Spartan-IIE ...
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... Interconnected as 1 CCO V Banks 8 independent REF See Xilinx Application Note XAPP179 on I/O resources. Hot Swap, Hot Insertion, Hot Socketing Support The I/O pins support hot swap — also called hot insertion and hot socketing — and are considered CompactPCI Friendly according to the PCI Bus v2.2 Specification. Con- ...
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... Product Specification Spartan-IIE 1.8V FPGA Family: Functional Description Similarly, the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the two F5-multiplexer outputs. This permits the implementation of any 6-input function, an 8:1 multiplexer, or selected func- tions inputs. www.xilinx.com 1-800-255-7778 5 ...
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... XC2S200E XC2S300E XC2S400E XC2S600E Each block RAM cell, as illustrated in chronous dual-ported 4096-bit RAM with independent con- trol signals for each port. The data widths of the two ports can be bus-width conversion. Dedicated www.xilinx.com 1-800-255-7778 Total Block RAM # of Blocks Bits 8 32K 10 40K 12 48K ...
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... ADDR<7:0> The Spartan-IIE block RAM also includes dedicated routing to provide an efficient interface with both CLBs and other block RAMs. See Xilinx Application Note information on block RAM. Programmable Routing It is the longest delay path that limits the speed of any design. Consequently, the Spartan-IIE routing architecture ...
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... Additional delay is introduced such that clock edges reach internal flip-flops exactly one clock period after they arrive at the input. This closed-loop system effectively eliminates clock-distribution delay by ensuring that clock www.xilinx.com 1-800-255-7778 Figure 8. CLB DS001_07_090600 ...
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... Spartan-IIE 1.8V FPGA Family: Functional Description DLL can delay the completion of the configuration process until after it has achieved lock. If the DLL uses external feed- back, apply a reset after startup to ensure consistent lock- ing to the external signal. See Xilinx Application Note XAPP174 Clock Distribution ...
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... Update, and Shift) that represent the StartupClk is TCK corresponding states in the boundary-scan internal state Enables BYPASS machine. Xilinx reserved Figure 12 instructions scan logic. It includes three bits of Data Register per IOB, the IEEE 1149.1 Test Access Port controller, and the Instruction Register with decodes ...
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... From a cavity-up view of the chip (as shown in the FPGA Editor), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in BSDL (Boundary Scan Description Language) files for Spartan-IIE family devices are available on the Xilinx web site at http://www.xilinx.com/support/sw_bsdl.htm Spartan-IIE boundary scan IDCODE values are shown in Table 7 ...
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... Configuration Configuration is the process by which the bitstream of a design, as generated by the Xilinx development software, is loaded into the internal configuration memory of the FPGA. Spartan-IIE devices support both serial configuration, using the master/slave serial and JTAG modes, as well as byte-wide configuration employing the Slave Parallel mode ...
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... Memory, page Once in user operation, the device can be re-configured simply by pulling the PROGRAM pin Low. The device acknowledges the beginning of the configuration process by driving DONE Low, then enters the memory-clearing phase. www.xilinx.com 1-800-255-7778 CCLK Direction Data Width Out ...
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... The start-up sequence oversees the transition of the FPGA from the configuration state to full user operation. A match of CRC values, indicating a successful loading of the config- FPGA Drives uration data, initiates the sequence. INIT Low Abort Start-up DS001_11_111501 www.xilinx.com 1-800-255-7778 Figure 16. Loading data using the Slave Figure 19, page 19. Clearing Con- Memory. ...
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... FPGA is configured by loading one bit per CCLK cycle. The MSB of each configuration data byte is always written to the DIN pin first. See Figure 16 Spartan-IIE FPGA serially. This is an expansion of the "Load Configuration Data Frames" block in page 14. www.xilinx.com 1-800-255-7778 Default Cycles Phase ...
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... Data on the DOUT pin changes on the rising edge of CCLK. DS001_14_032300 Note that DOUT changes on the falling edge of CCLK for some Xilinx families but mixed daisy chains are allowed. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are High. For more information, see Start-up, page 1 ...
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... R Master Serial Mode In Master Serial mode, the CCLK output of the FPGA drives a Xilinx PROM, which feeds a serial stream of configuration data to the FPGA’s DIN input. Figure 17 Serial FPGA configuring a Slave Serial FPGA from a PROM. A Spartan-IIE device in Master Serial mode should be connected as shown for the device on the left side. Mas- ter Serial mode is selected by a < ...
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... Acceptance will instead occur on the first clock after BUSY goes Low, and the data must be held until this happens. 3. Repeat steps 1 and 2 until all the data has been sent. 4. Deassert CS and WRITE. www.xilinx.com 1-800-255-7778 ...
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... The boundary-scan mode is selected by a <10x> on the mode pins (M0, M1, M2). Note that the PROGRAM pin must be pulled High prior to reconfiguration. A Low on the PRO- GRAM pin resets the TAP controller and no boundary scan operations can be performed. See Xilinx Application Note DS001_19_032300 XAPP188 ration. ...
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... Spartan-IIE 1.8V FPGA Family: Functional Description Revision History Version No. Date 1.0 11/15/01 Initial Xilinx release. 2.0 11/18/02 Added XC2S400E and XC2S600E. Removed Preliminary designation. Clarified details of I/O standards, boundary scan, and configuration. 2.1 07/09/03 Added hot swap description (see Table 7 The Spartan-IIE Family Data Sheet DS077-1, Spartan-IIE 1.8V FPGA Family: DS077-2, Spartan-IIE 1 ...
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... For soldering guidelines, see the Packaging Information on the Xilinx website. © 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. ...
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... Industrial XC2S200E Commercial Industrial XC2S300E Commercial Industrial XC2S400E Commercial Industrial XC2S600E Commercial Industrial (1) pin TQ, PQ, FG, FT packages = 0V 3.3V IN CCO = 3.6V (sample tested) IN www.xilinx.com 1-800-255-7778 Min Max 0 85 –40 100 1.8 – 1.8 – 1.2 3.6 1.2 3.6 - 250 –10%). For every 50 mV reduction in CCINT Min Typ Max 1 ...
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... CCPO 2. Devices built after the Product Change Notice PCN 2002-05 (see http://www.xilinx.com/bvdocs/notifications/pcn2002-05.pdf) have improved power-on requirements. Devices after the PCN have a ‘T’ preceding the date code as referenced in the PCN. Note that the XC2S150E, XC2S400E, and XC2S600E always have this mark. Devices before the PCN have an ‘S’ preceding the date code ...
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... Common-mode input voltage = 1.25 V Differential input voltage = ±350 mV LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. The following table summa- rizes the DC output specifications of LVPECL. Min Max 3.0 1.8 2.11 0.96 1.27 1.49 2.72 0.86 2.125 0.3 - www.xilinx.com 1-800-255-7778 Max V, Min mA 0.4 V – 0.4 24 CCO 0.4 V – 0.4 ...
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... Listed below are representative val- ues. For more specific, more precise, and worst-case guar- anteed data, use the values reported by the static timing analyzer (TRACE in the Xilinx Development System) and Global Clock Input to Output Delay for LVTTL, with DLL (Pin-to-Pin) Symbol ...
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... For a global clock input with standards other than LVTTL, adjust delays with values from the I/O Standard Global Clock Input Adjustments, page 6 Description (1) with DLL 12. Device XC2S50E XC2S100E (1) XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E 12. www.xilinx.com 1-800-255-7778 R Speed Grade -7 -6 Min Min Units 1 1 Speed Grade -7 -6 Min Min Units 1 ...
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... Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics (1) Standards, page Description Device All All All XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E All All XC2S50E XC2S100E XC2S150E XC2S200E XC2S300E XC2S400E XC2S600E All All All All www.xilinx.com 1-800-255-7778 8. Speed Grade -7 -6 Min Max Min 0.4 0.8 0.4 0.5 1.0 0.5 0.7 1.5 0.7 1.3 3.0 1.3 1.3 3.0 1.3 1.3 3.2 1.3 1.3 3 ...
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... ISSTL2 T ISSTL3 T ICTT T IAGP 8 Standard -7 LVTTL 0 LVCMOS2 0 LVCMOS18 0.20 LVDS 0.15 LVPECL 0.15 PCI, 33 MHz, 3.3V 0.08 PCI, 66 MHz, 3.3V –0.11 GTL 0.14 GTL+ 0.14 HSTL 0.04 SSTL2 0.04 SSTL3 0.04 CTT 0.10 AGP 0.04 www.xilinx.com 1-800-255-7778 R Speed Grade -6 Units 0.20 ns 0.15 ns 0.15 ns 0.08 ns –0.11 ns 0.14 ns 0.14 ns 0.04 ns 0.04 ns 0.04 ns 0.10 ns 0.04 ns DS077-3 (v2.1) July 9, 2003 Product Specification ...
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... SR input to valid data on pad (asynchronous) IOSRON T GSR to pad IOGSRQ Notes: 1. Three-state turn-off delays should not be adjusted. DS077-3 (v2.1) July 9, 2003 Product Specification Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Description (1) (1) (1) ( (1) www.xilinx.com 1-800-255-7778 Standards(1), page 10. Speed Grade -7 -6 Min Max Min Max 1.0 2.7 1.0 2.9 1.2 3.1 1.2 3.4 0.7 1.7 0.7 1.9 1 ...
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... LVPECL –0.41 PCI, 33 MHz, 3.3V 2.3 PCI, 66 MHz, 3.3V –0.41 GTL 0.49 GTL+ 0.8 HSTL I –0.51 HSTL III –0.91 HSTL IV –1.01 SSTL2 I –0.51 SSTL2 II –0.91 SSTL3 I –0.51 SSTL3 II –1.01 CTT –0.61 AGP –0.91 Methodology, page 11. www.xilinx.com 1-800-255-7778 R Speed Grade -6 Units 14.7 ns 7.5 ns 4.8 ns 3.0 ns 1.9 ns 1.7 ns 1.3 ns 13.1 ns 5.3 ns 3 – ...
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... Notes: 1. I/O parameter measurements are made with the capacitance and values shown above. Refer to Application Note appropriate terminations. 2. I/O standard measurements are reflected in the IBIS model information except where the IBIS format precludes it. XAPP179 for www.xilinx.com 1-800-255-7778 IOOP ( Standard (pF) 35 0.41 35 0. ...
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... Input timing for GPLVTTL is measured at 1.4V. For other I/O standards, see the table Delay Measurement 12 with the values shown in GPIO Description Standard LVTTL LVCMOS2 LVCMOS18 LVDS LVCPECL PCI, 33 MHz, 3.3V PCI, 66 MHz, 3.3V GTL GTL+ HSTL SSTL2 SSTL3 CTT AGP www.xilinx.com 1-800-255-7778 I/O Standard Global Clock Speed Grade -7 -6 Max Max Units 0.7 0.7 ns 0.45 0.5 ns Speed Grade -7 -6 Units 0 ...
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... MHz 1.5 ≥300 MHz 1.3 Figure 1, page 14, provides definitions for various parame- ters in the table below. CLKDLLHF F Min CLKIN - - (1) > 60 MHz - 50-60 MHz - 40-50 MHz - 30-40 MHz - 25-30 MHz - (2) - (3) - (4) - (5) - (6) - www.xilinx.com 1-800-255-7778 Speed Grade -6 Max Min Max Units 320 60 275 MHz 160 25 135 MHz - 1.8 ...
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... Output Jitter: the difference between an ideal reference clock edge and the actual design. Ideal Period Actual Period CLKIN + T IPTOL _ Phase Offset and Maximum Phase Difference Figure 1: Period Tolerance and Clock Jitter www.xilinx.com 1-800-255-7778 +/- Jitter + Maximum Phase Difference + Phase Offset DS001_52_090800 DS077-3 (v2.1) July 9, 2003 Product Specification R ...
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... CH T Pulse width, Low CL Set/Reset T Pulse width, SR/BY inputs RPW T Delay from SR/BY inputs to XQ/YQ outputs RQ (asynchronous) F Toggle frequency (for export control) TOG DS077-3 (v2.1) July 9, 2003 Product Specification Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Description www.xilinx.com 1-800-255-7778 Speed Grade -7 -6 Min Max Min Max 0.18 0.42 0.18 0.47 0.3 0.8 0.3 0.9 0.3 0.8 ...
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... G1/2 operand inputs to YB output via AND GANDYB T G1/2 operand inputs to COUT output via AND GANDCY Setup/Hold Times with Respect to Clock CLK CIN input to FFX CCKX CKCX CIN input to FFY CCKY CKCY 16 Description Min 1 1 www.xilinx.com 1-800-255-7778 Speed Grade -7 -6 Max Min Max - 0.8 - 0.8 - 0.8 - 0.9 - 1 ...
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... Clock CLK T Pulse width, High BPWH T Pulse width, Low BPWL T CLKA -> CLKB setup time for different ports BCCS DS077-3 (v2.1) July 9, 2003 Product Specification Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics Description Description Description www.xilinx.com 1-800-255-7778 Speed Grade -7 -6 Min Max Min Max 0.6 1.5 0.6 1.7 0.8 1.9 0.8 2 ...
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... Before configuration can begin, V CCINT 18 Description Description T POR T PL CCLK Output or Input M0, M1, M2 (Required) Description and V Bank 2 must reach the recommended operating voltage. CCO Figure 2: Configuration Timing on Power-Up www.xilinx.com 1-800-255-7778 Speed Grade -7 -6 Max Max 0 0 0.1 0.11 0.1 0.11 Speed Grade -7 -6 Min Max ...
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... CCLK High time Low time Maximum frequency Figure 3: Slave Serial Mode Timing T CKDS T DSCK T CCO Description DIN setup/hold DOUT Frequency tolerance with respect to nominal Figure 4: Master Serial Mode Timing www.xilinx.com 1-800-255-7778 T CCL DS001_16_032300 All Devices Min Max Units ...
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... BUSY Figure 6: Slave Parallel (SelectMAP) Mode Write Abort Waveforms 20 T SMCSCC T SMCCD Write No Write Description D0-D7 setup/hold CS setup/hold WRITE setup/hold BUSY propagation delay Frequency Frequency with no handshake Abort www.xilinx.com 1-800-255-7778 T SMCCCS T SMWCC Write DS001_20_061200 All Devices Min Max Units ...
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... R Revision History Version No. Date 1.0 11/15/01 Initial Xilinx release. 1.1 06/28/02 Added -7 speed grade and extended DLL specs to Industrial. 2.0 11/18/02 Added XC2S400E and XC2S600E. Added minimum specifications. Added reference to XAPP450 for Power-On Requirements. Removed Preliminary designation. 2.1 07/09/03 Added ICCINTQ typical values. Reduced ICCPO power-on current requirements. Relaxed TCCPO power-on ramp requirements ...
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... Spartan-IIE 1.8V FPGA Family: DC and Switching Characteristics 22 www.xilinx.com 1-800-255-7778 R DS077-3 (v2.1) July 9, 2003 Product Specification ...
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... Yes CCINT © 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS077-4 (2.1) February 14, 2003 ...
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... Module 2, Input Ground. All must be connected. See PCI core These signals can only be accessed when using Xilinx PCI cores. documentation If the cores are not used, these pins are available as user I/Os. Bidirectional Differential I/O with synchronous output positive negative ...
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... When VREF is only available in limited densities, the "Pad Name" column leaves out the VREF designation and the "VREF Option" column indicates the densities that pro- vide VREF on the given pin. www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables level must be the same for both banks. ...
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... VCCINT I/O, L18N_YY - - I/O, L18P_YY - - I/O, VREF Bank I/O (DLL), L17N XC2S50E - VCCINT XC2S50E All GCK1, I All - VCCO All - GND - - XC2S50E - GCK0, I XC2S50E XC2S100E I/O (DLL), L17P www.xilinx.com 1-800-255-7778 Pad Name LVDS Async. Output Bank Pin Option 6 P28 - 6 P29 - 6 P30 - 6 P31 All 6 P32 All - P33 - - P34 - - ...
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... Bank I/O - All I/O (DIN, D0), L6N_YY - - I/O (DOUT, BUSY), XC2S50E XC2S100E L6P_YY XC2S50E - CCLK - - VCCO All - TDO GND All - TDI - - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Pad Name LVDS Async. Output Bank Pin Option 3 P85 XC2S50E 3 P86 XC2S50E 3 P87 - - P88 - 3 P89 - - P90 - - P91 ...
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... GCK0 - - All - GCK1 All - GCK2 - All GCK3 - - - - - - - - - - - - - - - - - All All - All - - - - - All - All XC2S100E www.xilinx.com 1-800-255-7778 LVDS Async. Output Bank Pin Option 0 P139 - 0 P140 - 0 P141 - 0 P142 - - P143 - - P144 - P Bank Pin Name Pin 4 P55 GCK0, I P56 5 P52 GCK1, I P50 1 P126 GCK2, I P125 0 ...
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... I/O, L42P_YY - I/O, L42N_YY - - I/ L41P_YY - - I/O, All - L41N_YY VCCINT All - VCCO GND All - I/O, L40P All - I/O, L40N - - All I/O I/O - I/O www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables LVDS Async. Output Bank Pin Option 7 P22 - 7 P23 All 7 P24 All - P25 - - P26 - 6 P27 - - P28 - 6 P29 - 6 P30 XC2S50E, 300E ...
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... GCK0, I All All I/O (DLL), L31P I/O All - I/O, L30N - I/O, VREF Bank 4, - L30P GND XC2S100E, I/O, L29N 150E, 200E, 300E 300E I/O, L29P - 300E I/O, L28N - - www.xilinx.com 1-800-255-7778 LVDS Async. Output V Bank Pin Option Option - P66 - - P67 - 5 P68 XC2S50E, 100E, 200E, 300E 5 P69 XC2S50E, 100E, 200E, 300E ...
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... Bank 3, L19N I/O (D4 L19P - - I VCCINT All - I/O (TRDY) VCCO All - GND - XC2S200E, 300E I/O (IRDY L18N_YY I/O, L18P_YY www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables LVDS Async. Output Bank Pin Option 3 P111 XC2S50E, 150E, 200E, 300E 3 P112 XC2S50E, 150E, 200E, 300E 3 P113 - 3 P114 - 3 P115 XC2S50E, ...
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... I/O, L9P 300E 150E, 200E, 300E - - I/O, L9N - - - - GND All 150E VCCO VCCINT - I/O, L8P 150E - XC2S200E, 300E I/O, L8N All - I/O, L7P All - I/O, L7N - - GND www.xilinx.com 1-800-255-7778 LVDS Async. Output V Bank Pin Option Option - P156 - 2 P157 - - P158 - - P159 - 1 P160 All 1 P161 All 1 P162 - XC2S200E, 300E ...
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... TCK VCCO - - - - PQ208 Differential Clock Pins - - Clock - GCK0 All GCK1 - - GCK2 - GCK3 - - - - - - - - - - XC2S100E, 150E, 200E, 300E - - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables LVDS Async. Output Bank Pin Option 0 P201 - 0 P202 All 0 P203 All 0 P204 - 0 P205 - 0 P206 - - P207 - - P208 - P Bank Pin ...
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... I/O, L70N_YY - I/O, L69P All - I/O, L69N All - I/O, L68P_YY - 150E I/O, L68N_YY - I/O, L67P 150E All - I/O, L67N All - All I/O, L66P - I/O, L66N www.xilinx.com 1-800-255-7778 LVDS Async. Output V REF Bank Pin Option Option 7 H4 XC2S100E, 150E, 200E 7 H3 XC2S100E, XC2S400E 150E, 200E 7 H2 All 7 H1 All ...
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... I/O, L53P - I/O All - I/O (DLL), All - L52N All All GCK1, I GCK0, I All - I/O (DLL), - L52P 300E I/O, L51N www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables LVDS Async. Output Bank Pin Option 5 P6 XC2S50E, 100E, 150E, 300E 5 R6 XC2S50E, 100E, 200E, 300E, 400E 5 T6 ...
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... I/O, L39P XC2S100E, 150E, 200E, 300E, 400E I/O, VREF Bank 3, L38N - 300E I/O, L38P - 300E (2) I/O All - (2) I/O All All I/O, L36N All - I/O (D6), L36P All - www.xilinx.com 1-800-255-7778 LVDS Async. Output V REF Bank Pin Option Option 4 R13 XC2S50E, XC2S200E, 150E 300E, 400E 4 P13 XC2S50E, 150E 4 T14 All 4 R14 ...
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... XC2S400E I/O, L23N 400E I/O, L23P - - I/O, L22N All - I/O, VREF All - Bank 2, L22P XC2S400E I/O, L21N 400E - I/O, L21P 400E - I/O, L20N www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables LVDS Async. Output Bank Pin Option 2 F16 XC2S50E, 300E, 400E 2 H13 XC2S50E, 100E, 150E, 200E, (1) 300E 2 G14 ...
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... All All I/O (DLL), L8P GCK2, I All - GCK3 I/O (DLL), L8N 300E I/O - I/O, L7P 300E XC2S100E, I/O, VREF 150E, 200E, Bank 0, L7N 300E, 400E - www.xilinx.com 1-800-255-7778 LVDS Async. Output V REF Bank Pin Option Option 1 E10 XC2S50E, 100E, 200E, 300E, 400E 1 D10 XC2S50E, 100E, 200E, 300E, 400E ...
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... VCCO Bank 6 Pins All - J5 All - VCCO Bank 7 Pins All - G6 All XC2S200E, 300E, 400E GND Pins - - F11 R15 www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables P Bank Pin Name Pin 4 T9 GCK0 GCK1 GCK2 GCK3 ...
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... I/O, L84P_Y I/O, L110P - I/O, I/O, L110N L84N_Y All I/O, VREF I/O, VREF Bank 7, Bank 7, L83P L109P_Y - I/O, L83N I/O, L109N_Y - - I I/O, L108P_Y - I/O I/O, L108N_Y XC2S600E I/O, L82P_Y I/O, L107P_Y - I/O, I/O, L82N_Y L107N_Y www.xilinx.com 1-800-255-7778 200E 300E 400E TMS TMS TMS I/O I/O I/O - I/O I/O I/O I/O I/O I/O, I/O, I/O, L119P_Y L119P_Y L119P_Y I/O, I/O, I/O, L119N_Y L119N_Y L119N_Y I/O, VREF I/O, VREF I/O, VREF Bank 7, Bank 7, Bank 7, L118P_Y ...
Page 68
... All I/O, VREF I/O, VREF Bank 7, Bank 7, L77P L101P - I/O, L77N I/O, L101N - - - - - - - I/O, L76P_Y I/O, L100P_Y XC2S400E, I/O, I/O, 600E L76N_Y L100N_Y - - I www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables 200E 300E 400E - I/O I/O I/O, VREF I/O, VREF I/O, VREF Bank 7, Bank 7, Bank 7, L113P L113P_Y L113P_Y I/O, L113N I/O, I/O, L113N_Y L113N_Y I/O, I/O, I/O, L112P_YY L112P_YY L112P_YY I/O, I/O, I/O, L112N_YY ...
Page 69
... I/O, L72P_Y I/O, L96P_Y - I/O, I/O, L72N_Y L96N_Y - - - - - I/O, L95P_Y - I/O, L71P_Y I/O, L95N_Y - I/O, I/O, L94P_Y L71N_Y - - I/O, L94N_Y - - - - I/O, I/O, L70P_YY L93P_YY - I/O, I/O, L70N_YY L93N_YY www.xilinx.com 1-800-255-7778 200E 300E 400E I/O, I/O, I/O, L105P_YY L105P_YY L105P_YY I/O (IRDY), I/O (IRDY), I/O (IRDY), L105N_YY L105N_YY L105N_YY I/O (TRDY) I/O (TRDY) I/O (TRDY) - I/O I/O I/O, I/O, I/O, L104P L104P_Y L104P_Y I/O, I/O, I/O, VREF L104N_Y L104N_Y Bank 6, L104N I/O, L103P I/O, I/O, L103P_Y ...
Page 70
... I/O, I/O, L87N 300E, L65N_Y 400E, 600E - I/O I I/O, L86P - - I/O, L86N - - - - I/O, I/O, L64P_YY L85P_YY - I/O, I/O, L64N_YY L85N_YY - M1 M1 www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables 200E 300E 400E I/O, L97P I/O, L97P_Y I/O, L97P_Y I/O, L97P_Y I/O, VREF I/O, VREF I/O, VREF Bank 6, Bank 6, Bank 6, L97N L97N_Y L97N_Y - I/O I/O I/O I/O I/O I/O, L96P_Y I/O, L96P I/O, L96P_Y I/O, I/O, L96N I/O, L96N_Y L96N_Y ...
Page 71
... I/O, L61P_YY L81P_YY All I/O, VREF I/O, VREF Bank 5, Bank 5, L60N_YY L80N_YY - I/O, I/O, L60P_YY L80P_YY - - I I/O, L79N - I/O I/O, L79P XC2S600E I/O, I/O, L78N L59N_Y - I/O, L59P_Y I/O, L78P - - - www.xilinx.com 1-800-255-7778 200E 300E 400E I/O, I/O, I/O, L89N_Y L89N_Y L89N_Y - I/O I/O I/O I/O I/O I/O, I/O, I/O, L88N_Y L88N_Y L88N_Y I/O, L88P_Y I/O, L88P_Y I/O, L88P_Y I/O, L88P_Y I/O, VREF I/O, VREF I/O, VREF Bank 5, Bank 5, ...
Page 72
... I/O I/O, L71N XC2S400E, - I/O, L71P 600E - - - - I/O (DLL), I/O (DLL), L53N L70N - GCK1, I GCK1, I www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables 200E 300E 400E I/O, VREF I/O, VREF I/O, VREF Bank 5, Bank 5, Bank 5, L82N_Y L82N_Y L82N_Y I/O, L82P_Y I/O, L82P_Y I/O, L82P_Y I/O, L82P_Y I/O, I/O, I/O, L81N_Y L81N_Y L81N_Y I/O, L81P_Y I/O, L81P_Y I/O, L81P_Y I/O, L81P_Y ...
Page 73
... I/O, L65N_Y - - I/O, L65P_Y I/O, L69P_Y - I/O, I/O, L64N L48N_Y - I/O, L48P_Y I/O, L64P - I/O, I/O, L63N L47N_Y All I/O, VREF I/O, VREF Bank 4, Bank 4, L47P_Y L63P - - - - I/O I/O www.xilinx.com 1-800-255-7778 200E 300E 400E GCK0, I GCK0, I GCK0, I I/O (DLL), I/O (DLL), I/O (DLL), L75P L75P L75P - I/O I/O I/O, L74N I/O, I/O, L74N L74N_Y I/O, L74P I/O, L74P_Y I/O, VREF Bank 4, L74P I/O, L73N I/O, I/O, L73N L73N_Y ...
Page 74
... I/O, I/O, L42P_YY L56P_YY - DONE DONE - PROGRAM PROGRAM PROGRAM PROGRAM PROGRAM PROGRAM - I/O (INIT), I/O (INIT), L41N_YY L55N_YY - I/O (D7), I/O (D7), L41P_YY L55P_YY - - - - - I/O www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables 200E 300E 400E I/O, I/O, L66N I/O, L66N_Y L66N_Y I/O, L66P I/O, L66P_Y I/O, I/O, L65N I/O, L65N L65N_Y I/O, L65P I/O, L65P I/O, I/O, I/O, L64N_YY L64N_YY L64N_YY I/O, VREF ...
Page 75
... I/O, I/O, L37N_Y L49N_Y - I/O, L37P_Y I/O, L49P_Y - - - All I/O, VREF I/O, VREF Bank 3, Bank 3, L36N L48N - I/O (D6), I/O (D6), L36P L48P - I/O (D5), I/O (D5), L35N_YY L47N_YY - I/O, I/O, L35P_YY L47P_YY www.xilinx.com 1-800-255-7778 200E 300E 400E I/O, I/O, I/O, L58N_Y L58N_Y L58N_Y I/O, VREF I/O, VREF I/O, VREF Bank 3, Bank 3, Bank 3, L57N_Y L57N_Y L57N I/O, L57P_Y I/O, L57P_Y I/O, L57P - I/O I/O I/O I/O I/O I/O, I/O, I/O, L56N L56N_Y ...
Page 76
... I/O, I/O, L31N_Y L42N_Y XC2S400E, I/O, L31P_Y I/O, L42P_Y 600E - - I I/O (TRDY) I/O (TRDY) - I/O (IRDY), I/O (IRDY), L30N_YY L41N_YY - I/O, I/O, L30P_YY L41P_YY - - - - - I/O www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables 200E 300E 400E I/O I/O I/O I/O, I/O, I/O, L50N_Y L50N_Y L50N_Y I/O, I/O, I/O, L49N L49N_Y L49N_Y I/O, L49P I/O I/O I/O I/O, I/O, I/O, L48N L48N_YY L48N_YY I/O, I/O, I/O, L48P L48P_YY L48P_YY I/O, VREF I/O, VREF ...
Page 77
... I/O, L36P_Y - - - - I/O I/O, L35N_Y - I/O (D2) I/O (D2), L35P_Y - I/O (D1), I/O (D1), L26N L34N All I/O, VREF I/O, VREF Bank 2, Bank 2, L26P L34P - - - - I/O I/O www.xilinx.com 1-800-255-7778 200E 300E 400E I/O, L43P_Y I/O, L43P_Y I/O, VREF Bank 2, L43P I/O, L42N I/O, I/O, L42N_Y L42N_Y I/O, L42P I/O, L42P_Y I/O, L42P_Y - I/O I/O I/O (D3) I/O (D3) I/O (D3) I/O, VREF I/O, VREF I/O, VREF Bank 2, Bank 2, Bank 2, L41N_Y L41N L41N_Y I/O, L41P_Y ...
Page 78
... D0), L21N_YY L27N_YY - I/O (DOUT, I/O (DOUT, BUSY), BUSY), L21P_YY L27P_YY - CCLK CCLK - TDO TDO - TDI TDI - I/O (CS), I/O (CS), L20P_YY L26P_YY www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables 200E 300E 400E I/O, I/O, L35N I/O, L35N_Y L35N_Y I/O, L35P_Y I/O, L35P I/O, L35P_Y I/O, L35P_Y I/O, L34N I/O, I/O, L34N L34N_Y I/O, L34P I/O, L34P_Y I/O, L34P I/O, I/O, I/O, L33N_Y ...
Page 79
... I I/O, L21P - I/O I/O, L21N XC2S600E I/O, L16P_Y I/O, L20P - I/O, I/O, L20N L16N_Y - - - All I/O, VREF I/O, VREF Bank 1, Bank 1, L15P_Y L19P - I/O, I/O, L19N L15N_Y - I/O, L14P_Y I/O, L18P www.xilinx.com 1-800-255-7778 200E 300E 400E I/O I/O I/O (WRITE), (WRITE), (WRITE), L28N_YY L28N_YY L28N_YY - I/O I/O I/O I/O I/O I/O, L27P_Y I/O, L27P_Y I/O, L27P_Y I/O, L27P_Y I/O, I/O, I/O, L27N_Y L27N_Y L27N_Y I/O, VREF I/O, VREF I/O, VREF Bank 1, ...
Page 80
... I/O, L13P_Y 600E - - I/O, L13N_Y - - - - I/O (DLL), I/O (DLL), L9P L12P - GCK2, I GCK2 GCK3, I GCK3 I/O (DLL), I/O (DLL), L9N L12N - - - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables 200E 300E 400E I/O, I/O, I/O, L20N_Y L20N_Y L20N_Y I/O I/O I/O I/O, L19P I/O, L19P_Y I/O, L19P_Y I/O, L19P_Y I/O, L19N I/O, I/O, L19N_Y L19N_Y I/O, L18P I/O, L18P_Y I/O, L18P_Y I/O, L18P_Y I/O, L18N I/O, I/O, L18N_Y ...
Page 81
... I/O, L4P_Y I/O, L6P All I/O, VREF I/O, VREF Bank 0, Bank 0, L4N_Y L6N - - - - I/O I/O XC2S600E I/O, L3P I/O, L5P_Y - I/O, L3N I/O, L5N_Y - - I/O, L4P_Y - - I/O, L4N_Y www.xilinx.com 1-800-255-7778 200E 300E 400E I/O I/O I/O, VREF Bank 0 I/O, L12P I/O, L12P_Y I/O, L12P I/O, L12N I/O, I/O, L12N L12N_Y - I/O I/O I/O, L11P_Y I/O, L11P_Y I/O, L11P_Y I/O, L11P_Y I/O, VREF I/O, VREF I/O, VREF Bank 0, Bank 0, Bank 0, L11N_Y L11N_Y ...
Page 82
... TCK TCK P Pin Name AA12 GCK0, I AB12 GCK1, I A11 GCK2, I C11 GCK3, I E18 F6 R7 R16 (1) V18 W4 W19 G10 - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables 200E 300E 400E I/O, I/O, I/O, L3P_YY L3P_YY L3P_YY I/O, VREF I/O, VREF I/O, VREF Bank 0, Bank 0, Bank 0, L3N_YY L3N_YY L3N_YY I/O I/O I/O I/O, L2P ...
Page 83
... P13 P14 (2) (2) AA21 AA22 (1) (1) (1) D19 W4 LVDS Async. VREF Pin Output Option Option XC2S600E - D1 XC2S600E - E2 All - E1 All - E4 XC2S400E - www.xilinx.com 1-800-255-7778 - - - - - - - - - - - - - - - - - - - - - B21 C3 C20 J13 J14 K9 L9 L10 L11 M10 M11 M12 N12 N13 N14 T11 T12 Y20 AB1 AB22 ...
Page 84
... All All J1 All - K8 All - K7 All - All - K2 All - XC2S400E - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Device-Specific Pinouts XC2S400E XC2S600E I/O, L201N_Y I/O, L201N I/O, VREF Bank 7, I/O, VREF Bank 7, L200P L200P_Y I/O, L200N I/O, L200N_Y - I/O, L199P_Y I/O I/O, L199N_Y I/O, L198P_Y I/O, L198P I/O, L198N_Y I/O, L198N I/O, L197P I/O, L197P_Y I/O, L197N I/O, L197N_Y ...
Page 85
... All - N2 All - All - P2 All - P3 XC2S600E - P4 XC2S600E - P5 XC2S600E - P6 XC2S600E - XC2S600E - www.xilinx.com 1-800-255-7778 Device-Specific Pinouts XC2S400E XC2S600E I/O, L188N_Y I/O, L188N I/O, L187P I/O, L187P_Y I/O, L187N I/O, L187N_Y - I/O I/O, L186P I/O, L186P_Y I/O, L186N I/O, L186N_Y - I/O I/O, L185P I/O, L185P_Y I/O, L185N I/O, L185N_Y I/O, VREF Bank 7, I/O, VREF Bank 7, L184P_YY L184P_YY I/O, L184N_YY I/O, L184N_YY - I/O I/O, L183P_YY I/O, L183P_YY ...
Page 86
... V2 All - All All V5 All - V6 All - V7 All - XC2S600E - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Device-Specific Pinouts XC2S400E XC2S600E I/O, VREF Bank 6, I/O, VREF Bank 6, L176N L176N_Y I/O, L175P_Y I/O, L175P I/O, L175N_Y I/O, L175N - I/O I/O, L174P_YY I/O, L174P_YY I/O, L174N_YY I/O, L174N_YY - I/O I/O, L173P_YY I/O, L173P_YY I/O, VREF Bank 6, I/O, VREF Bank 6, ...
Page 87
... XC2S600E - AC3 All - AB4 All - AD1 - - AD2 - - AE1 All - AF2 All - AE3 - - AF3 - - AD4 - - www.xilinx.com 1-800-255-7778 Device-Specific Pinouts XC2S400E XC2S600E I/O, L164N I/O, VREF Bank 6, L164N_Y I/O, L163P_Y I/O, L163P I/O, L163N_Y I/O, L163N I/O I/O I/O, L162P_YY I/O, L162P_YY I/O, L162N_YY I/O, L162N_YY - I/O I/O, L161P_YY I/O, L161P_YY I/O, VREF Bank 6, I/O, VREF Bank 6, L161N_YY L161N_YY I/O I/O I/O, L160P_YY ...
Page 88
... Y9 XC2S600E - AA9 XC2S600E XC2S600E AB9 XC2S600E - AC9 All - AD9 All - AE9 All - AF9 All - All All www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Device-Specific Pinouts XC2S400E XC2S600E I/O I/O I/O I/O, L152N - I/O, L152P - I/O, L151N I/O I/O, L151P I/O, L150N_Y I/O, L150N I/O, L150P_Y I/O, L150P I/O, L149N_YY I/O, L149N_YY I/O, L149P_YY I/O, L149P_YY I/O, VREF Bank 5, ...
Page 89
... W13 - - Y13 XC2S600E - AA13 XC2S600E - AB13 XC2S600E All AC13 XC2S600E - AD13 - - V14 - - W14 - - AE13 - - AF13 - - www.xilinx.com 1-800-255-7778 Device-Specific Pinouts XC2S400E XC2S600E I/O, L138P_YY I/O, L138P_YY I/O, L137N_YY I/O, L137N_YY I/O, L137P_YY I/O, L137P_YY - I/O I/O, L136N I/O, L136N_Y I/O, L136P I/O, L136P_Y - I/O I/O, L135N_YY I/O, L135N_YY I/O, L135P_YY I/O, L135P_YY I/O, L134N_YY I/O, L134N_YY I/O, L134P_YY I/O, L134P_YY - I/O I/O, L133N I/O, L133N ...
Page 90
... All - All - All - All - - - Y17 XC2S600E - XC2S600E - - - All - All - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Device-Specific Pinouts XC2S400E XC2S600E GCK0, I GCK0, I I/O (DLL), L126P I/O (DLL), L126P - I/O I/O, L125N I/O, L125N I/O, L125P I/O, L125P - I/O I/O, L124N I/O, L124N_Y I/O, VREF Bank 4, I/O, VREF Bank 4, L124P L124P_Y I/O, L123N ...
Page 91
... All AB21 All - AA21 All - AF23 All - AE23 All - AD23 XC2S600E - AE24 XC2S600E - AF24 All - AF25 All - www.xilinx.com 1-800-255-7778 Device-Specific Pinouts XC2S400E XC2S600E I/O I/O I/O, VREF Bank 4, I/O, VREF Bank 4, L114N L114N I/O, L114P I/O, L114P I/O, L113N I/O, L113N I/O, L113P I/O, L113P I/O I/O I/O I/O, L112N_Y - I/O, VREF Bank 4, L112P_Y I/O, L111N I/O, L111N_Y ...
Page 92
... All - All - - - V19 XC2S400E - V20 XC2S400E - V21 XC2S600E XC2S600E V22 XC2S600E - V23 - - V24 All - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Device-Specific Pinouts XC2S400E XC2S600E DONE DONE PROGRAM PROGRAM I/O (INIT), L101N_YY I/O (INIT), L101N_YY I/O (D7), L101P_YY I/O (D7), L101P_YY - I/O, L100N - I/O, L100P - I/O, L99N_Y I/O I/O, L99P_Y I/O, L98N_YY I/O, L98N_YY ...
Page 93
... R26 All - P19 - - P20 XC2S400E - P21 XC2S400E - P22 XC2S600E All P23 XC2S600E - P24 - - P25 All - P26 All - www.xilinx.com 1-800-255-7778 Device-Specific Pinouts XC2S400E XC2S600E I/O, L88P_YY I/O, L88P_YY I/O I/O I/O, VREF Bank 3, I/O, VREF Bank 3, L87N_YY L87N_YY I/O (D6), L87P_YY I/O (D6), L87P_YY I/O (D5), L86N_YY I/O (D5), L86N_YY I/O, L86P_YY I/O, L86P_YY - I/O - I/O, L85N_Y I/O I/O, L85P_Y I/O I/O I/O, L84N_Y I/O, L84N ...
Page 94
... K26 XC2S600E - K25 XC2S600E - K24 - - K23 - - K22 - - K20 XC2S600E - K19 XC2S600E - J26 - - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Device-Specific Pinouts XC2S400E XC2S600E - I/O I/O (TRDY) I/O (TRDY) I/O (IRDY), L75N_YY I/O (IRDY), L75N_YY I/O, L75P_YY I/O, L75P_YY - I/O - I/O, L74N_Y I/O I/O, L74P_Y I/O I/O I/O, L73N I/O, L73N_Y I/O, VREF Bank 2, I/O, VREF Bank 2, L73P ...
Page 95
... E26 XC2S600E - E25 XC2S600E All E23 XC2S400E - E22 XC2S400E - F21 All - E21 All - D26 XC2S600E - D25 XC2S600E - www.xilinx.com 1-800-255-7778 Device-Specific Pinouts XC2S400E XC2S600E I/O, L64N_YY I/O, L64N_YY I/O (D2), L64P_YY I/O (D2), L64P_YY I/O (D1) I/O (D1) I/O, VREF Bank 2, I/O, VREF Bank 2, L63N_YY L63N_YY I/O, L63P_YY I/O, L63P_YY I/O, L62N_YY I/O, L62N_YY I/O, L62P_YY I/O, L62P_YY I/O I/O I/O I/O, L61N_Y ...
Page 96
... G19 All All F19 All - E19 - - B19 All - A19 All - H18 - - G18 XC2S600E - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Device-Specific Pinouts XC2S400E XC2S600E - I/O, L51N - I/O, L51P I/O (DIN, D0), I/O (DIN, D0), L50N_YY L50N_YY I/O (DOUT, BUSY), I/O (DOUT, BUSY), L50P_YY L50P_YY CCLK CCLK TDO TDO TDI ...
Page 97
... B15 All All A15 All - D15 - - J14 All - H14 All - G14 - - F14 XC2S600E - E14 XC2S600E - www.xilinx.com 1-800-255-7778 Device-Specific Pinouts XC2S400E XC2S600E I/O, L39N I/O, L39N_Y - I/O, VREF Bank 1, L38P_Y I/O I/O, L38N_Y I/O, L37P_YY I/O, L37P_YY I/O, L37N_YY I/O, L37N_YY I/O, L36P_YY I/O, L36P_YY I/O, L36N_YY I/O, L36N_YY I/O, VREF Bank 1, I/O, VREF Bank 1, L35P_YY L35P_YY ...
Page 98
... F11 All - C11 - - G11 - - H11 - - C10 - - A10 All - B10 All - D10 All - www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Device-Specific Pinouts XC2S400E XC2S600E I/O, VREF Bank 1, I/O, VREF Bank 1, L25P L25P_Y I/O, L25N I/O, L25N_Y - I/O I/O, L24P I/O, L24P I/O, L24N I/O, L24N - I/O I/O (DLL), L23P I/O (DLL), L23P GCK2, I GCK2, I ...
Page 99
... All - G7 All All All - B5 All All D5 All - www.xilinx.com 1-800-255-7778 Device-Specific Pinouts XC2S400E XC2S600E I/O, L14N_YY I/O, L14N_YY - I/O I/O, L13P I/O, L13P_Y I/O, L13N I/O, L13N_Y - I/O I/O, L12P_YY I/O, L12P_YY I/O, L12N_YY I/O, L12N_YY I/O I/O I/O, VREF Bank 0, I/O, VREF Bank 0, L11P L11P I/O, L11N I/O, L11N I/O, L10P I/O, L10P I/O, L10N I/O, L10N I/O I/O I/O I/O, L9P_Y - I/O, VREF Bank 0, ...
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... J18 L17 T10 V9 V18 D11 J10 D16 J16 K18 L18 T18 T23 V16 V17 V10 V11 www.xilinx.com 1-800-255-7778 Spartan-IIE 1.8V FPGA Family: Pinout Tables Device-Specific Pinouts XC2S400E XC2S600E I/O, L2N_YY I/O, L2N_YY I/O, L1P_YY I/O, L1P_YY I/O, L1N_YY I/O, L1N_YY I/O I/O, L0P_Y - I/O, L0N_Y I/O I/O TCK TCK N Input Pin ...
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... N19 N23 R4 R7 R19 U7 U24 U25 W12 W13 W14 AA7 AA9 AA22 AC1 AC15 AC22 AD10 AD11 AD13 AF4 AF16 AF18 www.xilinx.com 1-800-255-7778 C3 C12 F10 L11 L12 M12 N12 P12 P13 R13 T12 T13 W4 W23 AA10 AD3 AD12 AF26 C1 C2 D24 ...
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... R Revision History Version No. Date 1.0 11/15/01 Initial Xilinx release. 1.1 12/20/01 Corrected differential pin pair designations. 2.0 11/18/02 Added XC2S400E and XC2S600E and FG676. Removed L37 designation from FT256 pinouts. Minor corrections and clarifications to pinout definitions. Removed Preliminary designation. 2.1 02/14/03 Added differential pairs table on that XC2S50E has two VREF pins per bank. ...
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... Spartan-IIE 1.8V FPGA Family: Pinout Tables Module www.xilinx.com 1-800-255-7778 R DS077-4 (2.1) February 14, 2003 Product Specification ...