XCS05XL Xilinx, XCS05XL Datasheet
XCS05XL
Manufacturer Part Number
XCS05XL
Description
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Manufacturer
Xilinx
Datasheet
1.XCS05XL.pdf
(82 pages)
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DS060 (v1.6) September 19, 2001
Introduction
The Spartan
ume production FPGA solution that delivers all the key
requirements for ASIC replacement up to 40,000 gates.
These requirements include high performance, on-chip
RAM, core solutions and prices that, in high volume,
approach and in many cases are equivalent to mask pro-
grammed ASIC devices.
The Spartan series is the result of more than 14 years of
FPGA design experience and feedback from thousands of
customers. By streamlining the Spartan series feature set,
leveraging advanced process technologies and focusing on
total cost management, the Spartan series delivers the key
features required by ASIC and other high-volume logic
users while avoiding the initial cost, long development
cycles and inherent risk of conventional ASICs. The Spar-
tan and Spartan-XL families in the Spartan series have ten
members, as shown in
Spartan and Spartan-XL Features
Note: The Spartan series devices described in this data
sheet include the 5V Spartan family and the 3.3V
Spartan-XL family. See the separate data sheet for the 2.5V
Spartan-II family.
•
•
•
•
•
•
•
Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays
Notes:
1.
DS060 (v1.6) September 19, 2001
Product Specification
XCS05 and XCS05XL
XCS10 and XCS10XL
XCS20 and XCS20XL
XCS30 and XCS30XL
XCS40 and XCS40XL
First ASIC replacement FPGA for high-volume
production with on-chip RAM
Density up to 1862 logic cells or 40,000 system gates
Streamlined feature set based on XC4000 architecture
System performance beyond 80 MHz
Broad set of AllianceCORE™ and LogiCORE™
predefined solutions available
Unlimited reprogrammability
Low cost
Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
Device
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
™
and the Spartan-XL families are a high-vol-
Table
Logic
Cells
1368
1862
238
466
950
1.
R
System
10,000
20,000
30,000
40,000
Gates
5,000
Max
(Logic and RAM)
10,000-30,000
13,000-40,000
3,000-10,000
7,000-20,000
Gate Range
2,000-5,000
Typical
0
0
www.xilinx.com
1-800-255-7778
0
(1)
Spartan and Spartan-XL Families
Field Programmable Gate Arrays
Product Specification
•
•
Additional Spartan-XL Features
•
•
•
•
•
•
•
•
•
•
•
•
•
System level features
-
-
-
-
-
-
-
-
-
-
Fully supported by powerful Xilinx development system
-
-
-
3.3V supply for low power with 5V tolerant I/Os
Power down input
Higher performance
Faster carry logic
More flexible high-speed clock network
Latch capability in Configurable Logic Blocks
Input fast capture latch
Optional mux or 2-input function generator on outputs
12 mA or 24 mA output drive
5V and 3.3V PCI compliant
Enhanced Boundary Scan
Express Mode configuration
Chip scale packaging
10 x 10
14 x 14
20 x 20
24 x 24
28 x 28
Matrix
CLB
Available in both 5V and 3.3V versions
On-chip SelectRAM™ memory
Fully PCI compliant
Full readback capability for program verification
and internal node observability
Dedicated high-speed carry logic
Internal 3-state bus capability
Eight global low-skew clock or signal networks
IEEE 1149.1-compatible Boundary Scan logic
Low cost plastic packages available in all densities
Footprint compatibility in common packages
Foundation Series: Integrated, shrink-wrap
software
Alliance Series: Dozens of PC and workstation
third party development systems supported
Fully automatic mapping, placement and routing
CLBs
Total
100
196
400
576
784
Flip-flops
No. of
1,120
1,536
2,016
360
616
User I/O
Avail.
Max.
112
160
192
224
77
Distributed
RAM Bits
12,800
18,432
25,088
3,200
6,272
Total
1
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