LTC4266

Manufacturer Part NumberLTC4266
DescriptionQuad IEEE 802.3at Power over Ethernet Controller
ManufacturerLINER [Linear Technology]
LTC4266 datasheet
 
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FEATURES
Four Independent PSE Channels
n
Compliant with IEEE 802.3at Type 1 and 2
n
0.34Ω Total Channel Resistance
n
130mW/Port at 600mA
Advanced Power Management
n
8-Bit Programmable Current Limit (I
7-Bit Programmable Overload Currents (I
Fast Shutdown of Preselected Ports
14.5-Bit Port Current/Voltage Monitoring
2-Event Classification
Very High Reliability 4-Point PD Detection:
n
2-Point Forced Voltage
2-Point Forced Current
High Capacitance Legacy Device Detection
n
LTC4259A-1 and LTC4258 Pin and SW Compatible
n
2
1MHz I
C Compatible Serial Control Interface
n
Midspan Backoff Timer
n
Supports Proprietary Power Levels Above 25W
n
Available in 38-Pin 5mm × 7mm QFN and 36-Pin
n
SSOP Packages
APPLICATIONS
High Power PSE Switches/Routers
n
High Power PSE Midspans
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
TYPICAL APPLICATION
SCL
INT
SHDN1 SHDN2
SHDN3 SHDN4
SDAIN
SDAOUT
AD0
AD1
AD2
AD3
DGND
AGND V
SENSE1
GATE1 OUT1
EE
–50V
SMAJ58A
1µF
Quad IEEE 802.3at Power
over Ethernet Controller
DESCRIPTION
The LTC
4266 is a quad PSE controller designed for use
®
in IEEE 802.3 Type 1 and Type 2 (high power) compliant
Power over Ethernet systems. External power MOSFETs
enhance system reliability and minimize channel resis-
tance, cutting power dissipation and eliminating the need
)
for heatsinks even at Type 2 power levels. External power
LIM
)
components also allow use at very high power levels while
CUT
remaining otherwise compatible with the IEEE standard.
80V-rated port pins provide robust protection against
external faults.
The LTC4266 includes advanced power management
features, including current and voltage readback and pro-
grammable I
simplify power-management software development; an
optional AUTO pin mode provides fully IEEE-compliant
standalone operation with no software required. Proprietary
4-point PD detection circuitry minimizes false PD detec-
tion while supporting legacy phone operation. Midspan
operation is supported with built-in 2-event classification
and backoff timing. Host communication is via a 1MHz
2
I
C serial interface.
The LTC4266 is available in a 5mm × 7mm QFN package
that significantly reduces board space compared with
competing solutions. A legacy-compatible 36-pin SSOP
package is also available.
Complete 4-Port Ethernet High Power Source
3.3V
0.1µF
V
AUTO
MSD
RESET
DD
LTC4266
SENSE2 GATE2
OUT2
SENSE3 GATE3
OUT3
SENSE4 GATE4 OUT4
LTC4266
and I
thresholds. Available C libraries
CUT
LIM
MID
0.22µF 100V
S1B
S1B
×4
×4
×4
–50V
PORT1
PORT2
PORT3
PORT4
4266 TA01
4266fb
1

LTC4266 Summary of contents

  • Page 1

    ... Host communication is via a 1MHz serial interface. The LTC4266 is available in a 5mm × 7mm QFN package that significantly reduces board space compared with competing solutions. A legacy-compatible 36-pin SSOP package is also available. Complete 4-Port Ethernet High Power Source 3.3V 0.1µ ...

  • Page 2

    ... For more information on lead free part marking, go to: For more information on tape and reel specifications, go to: 2 Operating Temperature Range LTC4266C ................................................ 0°C to 70°C LTC4266I .............................................–40°C to 85°C Junction Temperature (Note 2) ............................. 125°C Storage Temperature Range .................. –65°C to 150°C Lead Temperature (Soldering, 10 sec) ................... 300° ...

  • Page 3

    ... Port Off GATEn EE Port Off GATEn GATEn EE V – 1µA GATEn EE GATEn V – V OUTn EE 0V ≤ (AGND – ≤ 5V OUTn LTC4266 – DGND = 3.3V unless DD MIN TYP MAX UNITS 3.0 3 ...

  • Page 4

    ... LTC4266 ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T otherwise noted. (Notes 3, 4) SYMBOL PARAMETER Current Sense V Overcurrent Sense Voltage CUT Overcurrent Sense in AUTO pin mode V Active Current Limit in 802.3af Compliant LIM Mode V Active Current Limit in High Power Mode LIM V Active Current Limit in AUTO pin mode ...

  • Page 5

    ... START0 (Notes 7, 12) ICUT1 ICUT0 (Note 7) Current Pulse Width to Reset Disconnect Timer (Notes [1:0] = 00b (Notes 5, 12) conf (Note 7) (Note 7) (Note 7) (Note 7) (Note 7) LTC4266 – DGND = 3.3V unless DD MIN TYP MAX UNITS 270 290 310 ms l 300 470 ...

  • Page 6

    ... Note 3: All currents into device pins are positive; all currents out of device pins are negative. Note 4: The LTC4266 operates with a negative supply voltage (with respect to ground). To avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. ...

  • Page 7

    ... V Supply Current vs Voltage EE 2.4 2.3 2.2 2.1 –40°C 25°C 85°C 2.0 –60 –55 –50 –45 –40 –35 –30 –25 –20 4 SUPPLY VOLTAGE (V) LTC4266 802.3af Classification in AUTO Pin Mode GND LOAD FULLY CHARGED –18.4 PORT PORT 1 VOLTAGE V = 3.3V DD 10V/DIV V = –55V CLASS 1 ...

  • Page 8

    ... LTC4266 TYPICAL PERFORMANCE CHARACTERISTICS 802.3af I Threshold vs LIM Temperature 108. 3. –54V 0.25 SENSE REG 48h = 80h 107.25 PORT 1 106.50 105.75 105.00 – TEMPERATURE (°C) 802.3af I Threshold vs CUT Temperature 96. 3. –54V 0.25 SENSE REG 47h = D4h 95.25 PORT 1 94.50 93.75 93.00 – TEMPERATURE (°C) ...

  • Page 9

    ... ADC OUTPUT PORT VOLTAGE 20V/DIV GATE VOLTAGE 10V/DIV PORT CURRENT 500mA/DIV 4266 G23 LTC4266 ADC Noise Histogram Port Voltage Readback in Fast Mode 600 AGND – 48.3V OUTn 500 400 300 200 100 0 260 261 262 450 500 263 ...

  • Page 10

    ... LTC4266 TEST TIMING DIAGRAMS V PORTn V INT Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-Auto Modes V LIM V CUT SENSEn EE 0V INT Figure 2. Current Limit Timing V GATEn t MSD t SHDN MSD or SHDNn 4266 F04 Figure 4. Shut Down Delay Timing 10 t CLASSIFICATION DET ...

  • Page 11

    ... R/W ACK AD3 AD2 AD1 AD0 ACK BY SLAVE FRAME 1 FRAME 2 ALERT RESPONSE ADDRESS BYTE SERIAL BUS ADDRESS BYTE Figure 9. Reading from Alert Response Address LTC4266 ACK ACK BY STOP BY SLAVE MASTER FRAME 3 DATA BYTE 4266 F06 ...

  • Page 12

    ... LTC4266 PIN FUNCTIONS RESET: Chip Reset, Active Low. When the RESET pin is low, the LTC4266 is held inactive with all ports off and all internal registers reset to their power-up states. When RESET is pulled high, the LTC4266 begins normal opera- tion. RESET can be connected to an external capacitor or RC network to provide a power turn-on delay. Internal filtering of the RESET pin prevents glitches less than 1µ ...

  • Page 13

    ... GATE1: Port 1 Gate Drive. See GATE 4. OUT1: Port 1 Output Voltage Monitor. See OUT4. AUTO: AUTO Pin Mode Input. AUTO pin mode allows the LTC4266 to detect and power even if there is no host controller present on the I AUTO pin determines the state of the internal registers when the LTC4266 is reset or comes out of V (see the Register map) ...

  • Page 14

    ... RJ45-style network connector. The LTC4266 is a third-generation quad PSE controller that implements four PSE ports in either an endpoint or midspan design. Virtually all necessary circuitry is included to implement a IEEE 802 ...

  • Page 15

    ... LTC425x chips always used 0.5Ω. To maintain compatibility, if the AUTO pin is low when the LTC4266 powers up it assumes the sense resistor is 0.5Ω high at power up, the LTC4266 assumes 0.25Ω. The resistor value setting can be reconfigured at any time after power up. In particular, systems that use 0.25Ω ...

  • Page 16

    ... CLASS Class 1 Class 2 Class 3 or Class 0 Class 4 The automatic setting of the I curs if the LTC4266 is reset with the AUTO pin high. CUT DETECTION Detection Overview To avoid damaging network devices that were not designed to tolerate DC voltage, a PSE must determine whether the connected device is a real PD before applying power. The IEEE specification requires that a valid PD have a common mode resistance of 25k ± ...

  • Page 17

    ... Figure 11). 4-Point Detection The LTC4266 uses a 4-point detection method to discover PDs. False-positive detections are minimized by check- ing for signature resistance with both forced-current and forced-voltage measurements. Initially, two test currents are forced onto the port (via the OUTn pin) and the resulting voltages are measured ...

  • Page 18

    ... PDs in this range of capacitance are defined as invalid PSE that detects legacy PDs is technically noncompliant with the IEEE spec. The LTC4266 can be configured to detect this type of legacy PD. Legacy detection is disabled by default, but can be manually enabled on a per-port basis. When enabled, the port will report detect good when it sees either a valid IEEE high-capacitance legacy PD ...

  • Page 19

    ... LTC4266. A Type 2 PD that is requesting more than 13W will indicate Class 4 during normal 802.3af classifi- cation. If the LTC4266 sees Class 4, it forces the port to a specified lower voltage (called the mark voltage, typically 9V), pauses briefly, and then re-runs classification to verify the Class 4 reading (Figure 1) ...

  • Page 20

    ... C0 0.7 CA 0.6 D0 0.5 DA 0.4 E0 0.3 0.2 49 0 Figure 15. LTC4266 Foldback vs FET Safe Operating 60 Area at 90°C Ambient 52 register settings. LIM 802.3af FOLDBACK SOA DC AT 90° VOLTAGE ( 58V PSE 4266 F14 802.3af FOLDBACK SOA DC AT 90° ...

  • Page 21

    ... Each port can be configured to high or low priority; all low-priority ports will shut down within 6.5μs after the MSD pin is pulled low. If multiple ports in a LTC4266 device are shut down via MSD, they are staggered by at least 0.55μs to help reduce voltage transients on the main ...

  • Page 22

    ... The LTC4266’s primary serial bus address is 010xxxxb, with the lower four bits set by the AD3-AD0 pins; this allows LTC4266s on a single bus. All LTC4266s also respond to the address 0110000b, allowing the host to write the same command (typically configuration commands) to multiple LTC4266s in a single transaction ...

  • Page 23

    ... V supply and possibly causing EE the LTC4266 to reset due to a UVLO fault. A 1μF , 100V X7R capacitor placed near the minimize spurious resets. Isolating the Serial Bus The LTC4266 includes a split SDA pin (SDAIN and SDAOUT) to ease opto-isolation of the bidirectional SDA line ...

  • Page 24

    ... AD3 DGND AGND 0.1µF LTC4266 V DD INT SCL SDAIN SDAOUT AD0 0100010 AD1 AD2 AD3 DGND AGND • 0.1µF • • LTC4266 V DD INT SCL SDAIN SDAOUT 0101110 AD0 AD1 AD2 AD3 DGND AGND 0.1µF LTC4266 V DD INT SCL SDAIN SDAOUT ...

  • Page 25

    ... SENSE and V the voltage drop across R R introduces errors. M bypass EE The example on the right shows how errors can be minimized with a good layout. The circuit is rearranged so that R to the LTC4266 is used as a Kelvin sense trace LTC4266 GATE SENSE + V ...

  • Page 26

    ... LTC4266 APPLICATIONS INFORMATION a perfect Kelvin connection because all four ports con- trolled by the LTC4266 share the same sense trace, and because the current through the trace (I However, as the equation shows, the remaining error is a small offset term. Figure 20 shows two LTC4266 chips controlling eight ports (A though H). The ports are separated into two groups of four ...

  • Page 27

    ... BSC * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE LTC4266 SENSE FOUR LARGE VIAS TO V PLANE EE HOLE IN V PLANE ...

  • Page 28

    ... LTC4266 PACKAGE DESCRIPTION 5.50 ± 0.05 4.10 ± 0.05 3.00 REF APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 7.00 ± 0.10 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 28 UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 5.15 ± ...

  • Page 29

    ... Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC4266 PAGE NUMBER ...

  • Page 30

    ... IEEE 802.3at PD Interface Integrated Switching Regulator 30 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 ● ISOLATED 3.3V 0.1µF DGND AGND SCL 1/4 SDAIN LTC4266 SDAOUT INT V SENSE GATE OUT EE 2k 1µF 100V R S X7R 0.25 SMAJ58A S1B –48V U3 ISOLATED ...