LTC4266 LINER [Linear Technology], LTC4266 Datasheet - Page 22

• Manufacturer Part Number: LTC4266
• Description: Quad IEEE 802.3at Power over Ethernet Controller
• Manufacturer: LINER [Linear Technology]

LTC4266
APPLICATIONS INFORMATION
supply. If a port is turned off via MSD, the corresponding
detection and classification enable bits are cleared, so
the port will remain off until the host explicitly re-enables
detection.
SERIAL DIGITAL INTERFACE
Overview
The LTC4266 communicates with the host using a standard
SMBus/I
device, and communicates with the host master using
the standard SMBus protocols. Interrupts are signaled to
the host via the INT pin. The timing diagrams (Figures 5
through 9) show typical communication waveforms and
their timing relationships. More information about the
SMBus data protocols can be found at www.smbus.org.
The LTC4266 requires both the V
to be present for the serial interface to function.
Bus Addressing
The LTC4266’s primary serial bus address is 010xxxxb, with
the lower four bits set by the AD3-AD0 pins; this allows up
to 16 LTC4266s on a single bus. All LTC4266s also respond
to the address 0110000b, allowing the host to write the
same command (typically configuration commands) to
multiple LTC4266s in a single transaction. If the LTC4266
is asserting the INT pin, it will also respond to the alert
response address (0001100b) per the SMBus spec.
Interrupts and SMBALERT
Most LTC4266 port events can be configured to trigger
an interrupt, asserting the INT pin and alerting the host to
the event. This removes the need for the host to poll the
LTC4266, minimizing serial bus traffic and conserving host
CPU cycles. Multiple LTC4266s can share a common INT
line, with the host using the SMBALERT protocol (ARA)
to determine which LTC4266 caused an interrupt.
Register Description
For information on serial bus usage and device configura-
tion and status, refer to the LTC4266 Software Program-
ming documentation.
22
2
C 2-wire interface. The LTC4266 is a slave-only
DD
and V
EE
supply rails
EXTERNAL COMPONENT SELECTION
Power Supplies and Bypassing
The LTC4266 requires two supply voltages to operate. V
requires 3.3V (nominally) relative to DGND. V
negative voltage of between –44V and –57V for Type 1 PSEs,
or –50V to –57V for Type 2 PSEs, relative to AGND. The
relationship between the two grounds is not fixed; AGND
can be referenced to any level from V
it should typically be tied to either V
V
cuitry, and draws a maximum of 3mA. A ceramic decoupling
cap of at least 0.1μF should be placed from V
as close as practical to each LTC4266 chip.
Figure 16 shows a three component low dropout regulator
for a negative supply to DGND generated from the negative
V
referenced to AGND. This regulator drives a single LTC4266
device. In Figure 17, DGND is tied to AGND in this boost
converter circuit for a positive V
AGND. This circuit can drive multiple LTC4266 devices
and opto couplers.
V
Because it supplies a relatively large amount of power and
is subject to significant current transients, it requires more
design care than a simple logic supply. For minimum IR
loss and best system efficiency, set V
amplitude (57V), leaving enough margin to account for
transient over- or undershoot, temperature drift, and the line
regulation specs of the particular power supply used.
DD
EE
EE
supply. V
is the main supply that provides power to the PDs.
provides power for most of the internal LTC4266 cir-
CMHZ4687-4.3V
AGND
DD
Figure 16. Negative LDO to DGND
V
EE
is tied to AGND and DGND is negative
750k
D1
R5
0.1µF
C1
Q2
CMPTA92
DD
supply of 3.3V above
V
DGND
DD
DD
DD
to DGND, although
LTC4266
EE
or DGND.
AGND
V
near maximum
EE
4266 F16
DD
EE
requires a
to DGND,
4266fb
DD