HSP43220/883 INTERSIL [Intersil Corporation], HSP43220/883 Datasheet

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HSP43220/883

Manufacturer Part Number
HSP43220/883
Description
Decimating Digital Filter
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
Decimating Digital Filter
The HSP43220/883 Decimating Digital Filter is a linear
phase low pass decimation filter which is optimized for
filtering narrow band signals in a broad spectrum of a signal
processing applications. The HSP43220/883 offers a single
chip solution to signal processing application which have
historically required several boards of ICs. This reduction in
component count results in faster development times, as
well as reduction of hardware costs.
The HSP43220/883 is implemented as a two stage filter
structure. As seen in the Block Diagram, the first stage is a
High Order Decimation Filter (HDF) which utilizes an
efficient decimation (sample rate reduction) technique to
obtain decimation up to 1024 through a coarse low-pass
filtering process. The HDF provides up to 96dB aliasing
rejection in the signal pass band. The second stage consists
of a Finite Impulse Response (FIR) decimation filter
structured as a transversal FIR filter with up to 512
symmetric taps which can implement filters with sharp
transition regions. The FIR can perform further decimation
by up to 16 if required, while preserving the 96dB aliasing
attenuation obtained by the HDF. The combined total
decimation capability is 16,384.
The HSP43220/883 accepts 16-bit parallel data in 2’s
complement format at sampling rates up to 30MSPS. It
provides a 16-bit microprocessor compatible interface to
simplify the task of programming and three-state outputs to
allow the connection of several ICs to a common bus. The
HSP43220/883 also provides the capability to bypass either
the HDF or the FIR for additional flexibility.
Block Diagram
CONTROL AND COEFFICIENTS
TM
1
INPUT CLOCK
DATA INPUT
Data Sheet
16
16
DECIMATION UP TO 1024
DECIMATE™ is a trademark of Intersil Corporation. IBM PC, XT, AT, PS/2™ are trademarks of IBM Corporation.
HIGH ORDER
DECIMATION
FILTER
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Features
• This Circuit is Processed in Accordance to MIL-STD-883
• Single Chip Narrow Band Filter with up to 96dB
• DC to 25.6MHz Clock Rate
• 16-Bit 2’s Complement Input
• 20-Bit Coefficients in FIR
• 24-Bit Extended Precision Output
• Programmable Decimation up to a Maximum of 16,384
• Standard 16-Bit Microprocessor Interface
• Filter Design Software Available DECI•MATE™
Applications
• Very Narrow Band Filters
• Zoom Spectral Analysis
• Channelized Receivers
Ordering Information
HSP43220GM-15/883
HSP43220GM-25/883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Attenuation
PART NUMBER
DECIMATION UP TO 16
DECIMATION
FIR CLOCK
March 1999
FILTER
FIR
|
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Intersil (and design) is a trademark of Intersil Americas Inc.
RANGE (
-55 to 125
-55 to 125
24
TEMP.
DATA OUT
DATA READY
HSP43220/883
o
C)
84 Ld PGA
84 Ld PGA
PACKAGE
FN2802.3
G84.A
G84.A
PKG.
NO.

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HSP43220/883 Summary of contents

Page 1

... ICs. This reduction in component count results in faster development times, as well as reduction of hardware costs. The HSP43220/883 is implemented as a two stage filter structure. As seen in the Block Diagram, the first stage is a High Order Decimation Filter (HDF) which utilizes an efficient decimation (sample rate reduction) technique to obtain decimation up to 1024 through a coarse low-pass filtering process ...

Page 2

... NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 8mA/MHz. 4. Tested as follows 1MHz 2. HSP43220/883 Thermal Information Thermal Resistance (Typical, Note 1) 0.5V PGA Package Maximum Package Power Dissipation at 125 PGA Package ...

Page 3

... Inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are CC made at 1.5V for both a Logic “1” and “0”. CLK is driven at 4.0V and 0V and measured at 2.0V. 6. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and C 3 HSP43220/883 GROUP A SUB- o GROUPS ...

Page 4

... Loading is as specified in the test load circuit with C 9. Applies only when H_BYP = 1 or H_DRATE = 0. CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D 4 HSP43220/883 TEST CONDITIONS NOTES -55 ≤ -55 ≤ -55 ≤ -55 ≤ T ...

Page 5

... A10 GND GND A11 GND GND B1 STARTIN F15 B2 STARTOUT DATA_IN DATA_IN DATA_IN HSP43220/883 HSP43220/883 TOP VIEW PINS DOWN DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ ...

Page 6

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 HSP43220/883 BURN-IN CIRCUIT SIGNALS (CONTINUED) PIN LEAD PIN NAME ...

Page 7

Ceramic Pin Grid Array Packages (CPGA INDEX CORNER b1 SEE NOTE 9 SEE NOTE 7 A 0.008 C –C– SECTION A Ø0.030 Ø0.010 M C ...

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