PCM1738E2K BURR-BROWN [Burr-Brown Corporation], PCM1738E2K Datasheet - Page 25

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PCM1738E2K

Manufacturer Part Number
PCM1738E2K
Description
24-Bit, 192kHz Sampling, Advanced Segment, Audio-Stereo DIGITAL-TO-ANALOG CONVERTER
Manufacturer
BURR-BROWN [Burr-Brown Corporation]
Datasheet
PCM1738
FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL-FILTER MODE
The external Digital-Filter mode allows access to the majority of the PCM1738’s mode control functions. Table IV shows the
register mapping available when the external Digital-Filter mode is selected, along with descriptions of functions that are modified
for this mode selection.
TABLE IV. Register Mapping in the External Digital-Filter Mode.
FMT[2:0]
OS[1:0]
ZFGx
NOTE: (1) This bit is required for selection of the external Digital-Filter mode. (2) “–” = function disabled.
REGISTER
SBAS174B
16
17
18
19
20
21
W/R
W/R
W/R
W/R
W/R
B15
When x = L or R, corresponding to the DAC output channel.
These bits are available only for Read back.
Default Value: 00
Audio Data Format Selection
These bits are available for Read/Write.
Default Value: 000
Delta-Sigma Oversampling Rate Selection
These bits are available for Read/Write.
Default Value: 00
Zero Detection Flag
When the PCM1738 detects that audio input data is continuously zero for 1024f
the corresponding channel(s). Zero detect flags are also available at ZEROL (pin 2) and ZEROR (pin 3).
R
The effective oversampling rate is determined by the oversampling performed by both the external digital filter
and the delta-sigma modulator. For example, if the external digital filter is 8x oversampling, and the user selects
OS[1:0] = 0, then the delta-sigma modulator will oversample by 8x, resulting in an effective oversampling rate
of 64x.
FMT[2:0]
OS[1:0]
ZFGx = 0
ZFGx = 1
Other
000
001
010
B14
00
01
10
11
0
0
0
0
0
0
B13
0
0
0
0
0
0
Audio Data Format Select
16-Bit Right Justified Format (default)
20-Bit Right Justified Format
24-Bit Right Justified Format
N/A
Operation Speed Select
8x f
Reserved
16x f
4x f
Not ZERO
ZERO Detected
B12
1
1
1
1
1
1
WCK
WCK
WCK
(default)
B11
0
0
0
0
0
0
B10
0
0
0
0
1
1
B9
0
0
1
1
0
0
B8
0
1
0
1
0
1
RSV
RSV
B7
FMT2
SRST
RSV
B6
MRST DFTH
FMT1
RSV
B5
FMT0
OPE
RSV
B4
(1)
S
, the ZFGx bit is set to 1 for
CLKD
RSV
RSV
B3
CLKE
CHSL
RSV
B2
DME
ZFGR
OS1
B1
(1)
ZFGL
INZD
OS0
B0
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