ICL7134BJCJI INTERSIL [Intersil Corporation], ICL7134BJCJI Datasheet
ICL7134BJCJI
Related parts for ICL7134BJCJI
ICL7134BJCJI Summary of contents
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... Two resistors which facilitate the reference inversion are included on the chip, so only an external op-amp is needed. The PROM is coded to correct for errors in these resistors as well as the inversion of the MSB. TEMPERATURE RANGE ( - ICL7134BJCJI ICL7134BJIJI ICL7134BKCJI ICL7134BKIJI ICL7134BLCJI ICL7134BLIJI ICL7134UJCJI ...
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Pinout Functional Block Diagram ICL7134 ICL7134 (OUTLINE DWG JI) TOP VIEW (LSB OUT AGND ...
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Pin Descriptions 28 LEAD PIN CERDIP NAME 1 CS Chip Select (active low). Enables register write WRITE, (active low). Writes in register. Equivalent to CS Bit 0 Least Significant Bit1 ...
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Absolute Maximum Ratings (Note 1) Supply Voltage (V+ to DGND -0.3V to 7.5V to DGND . . . . . . ...
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Electrical Specification V+ = +5V, V Unless Otherwise Specified. (Continued) PARAMETER REFERENCE INPUT Input Resistance RFL ANALOG OUTPUT Output Capacitance DAC Register Outputs All LOW (I Terminal) OUT DAC Register Outputs All HIGH DIGITAL INPUTS Low State ...
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Test Circuits FIGURE 2. POWER SUPPLY REJECTION TEST CIRCUIT ICL7134 FIGURE 1. NON-LINEARITY TEST CIRCUIT 6 ...
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Test Circuits (Continued) FIGURE 3. FEEDTHROUGH ERROR TEST CIRCUIT FIGURE 4. OUTPUT CURRENT SETTLING TIME TEST CIRCUIT Timing Diagrams FIGURE 5A. USING 14-BIT TRANSPARENT ADDRESSING ICL7134 7 ...
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Timing Diagrams FIGURE 5B. USING FULL BUFFER 8-BIT ADDRESSING CAPABILITY ICL7134 8 ...
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Definition of Terms Nonlinearity - Error contributed by deviation of the DAC transfer function from a straight line through the end points of the actual plot of transfer function. Normally expressed as a percentage of full scale range or in ...
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Digital Section Two levels of input buffer registers allow loading of data from an 8-bit or 16-bit data bus. The A and A 0 four operations: 1) load the LS-buffer register with the data at inputs ...
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For applications where the output reference ground point is established somewhere other than at the DAC, the circuit of Figure 9 can be used. ...
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FIGURE 10. BIPOLAR (2’S COMPLEMENT), FOUR-QUADRANT MULTIPLYING CIRCUIT Offset Adjustment 1. Connect all data inputs and WR, CS, A DGND. 2. Adjust the offset zero-adjust trim-pot of the operational , if used, for a maximum of 0V ±50µV at amplifier ...
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FIGURE 11. ICL7134 INTERFACE TO 8048 SYSTEM FIGURE 13. 8085 SYSTEM INTERFACE ICL7134 FIGURE 12. INTERFACE TO 8080 SYSTEM 13 ...
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FIGURE 14. R650X AND MC680X FAMILIES’ INTERFACE TO ICL7134 FIGURE 16. ICL7134 TO 8048/80/85 INTERFACE WITH LOW FEEDTHROUGH Digital Feedthrough All of the direct interfaces shown above can suffer from a capacitive coupling problem. The 14 data pins, and 4 ...
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ICL7134 FIGURE 17. SUCCESSIVE APPROXIMATION A/D CONVERTER 15 ...
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FIGURE 18A. PRONTED CIRCUIT SIDE OF CARD (SINGLE SIDED BOARD) FIGURE 18. PRINTED CIRCUIT BOARD LAYOUT (BIPOLAR CIRCUIT, SEE FIGURE 10) PC Board Layout Great care should be taken in the board layout to minimize ground loop and similar “hidden ...